[Coco] Re : 512KB SRAM upgrade

[jdaggett at gate.net]

Thanks Mike

I did reread the 41256 and the 4164 specs and if the GIME is doing RAS only 
refresh then Sylvain's circuit then  has no issues with refresh. RAS only refresh 
just activates the row address and the  RAS line. WE line needs to remain at logic 
"1".

What I might think of doing is code the circuit into webpack ISE and run the 
simulator and look at timing. A good practice and a way to test the circuit prior to 
committing to  hardware. 

james

On 24 Nov 2006 at 11:06, Mike Pepe wrote:

> jdaggett at gate.net wrote:
> > Sylvain
> > 
> > I seriously doubt that the WE0 and WE1 lines remain high suring refresh. In order 
> > to do a refresh the row address is placed on the DRAM address lines and then the 
> > RAS and WE lines are pulled low. 
> > 
> > james
> > 
> 
> Refresh cycles are reads, not writes. Just google and download any 
> 4164/41256/etc datasheet and check the refresh timing diagrams.
> 
> The refresh cycles would be pointless but probably not dangerous.
> 
> -Mike
> 
> 
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