[Coco] Re : Re : 512KB SRAM upgrade

[Sylvain Rousseau]

So it would be better to change the WE0/WE1 two inputs AND gate that make the WE for the SRAM for a 3 inputs AND gate, invert CAS and use it as the third input of the new 3 inputs AND gate?

So, the write to SRAM will be enable only when (WE0 OR WE1 are low) AND (CAS is low).

Sylvain


----- Message initial ----
De : "jdaggett at gate.net" <jdaggett at gate.net>
À : CoCoList for Color Computer Enthusiasts <coco at maltedmedia.com>
Envoyé le : jeudi 23 novembre 2006, 15 h 25 min 58 s
Objet : Re: [Coco] Re : 512KB SRAM upgrade


Sylvain

I seriously doubt that the WE0 and WE1 lines remain high suring refresh. In order 
to do a refresh the row address is placed on the DRAM address lines and then the 
RAS and WE lines are pulled low. 

james

On 23 Nov 2006 at 10:23, Sylvain Rousseau wrote:

> Thank you James.
> 
> I don't have a scope at home to look at GIME refresh sequence.  I hope WE0 and WE1 stay high during the refresh so the WE signal to the SRAM will be high too and no write to SRAM will occure during refresh. I will look on the web if I can find more infomations on it.
> 
> If you find something, please let me know.
> 
> Best Regards,
> 
> Sylvain
> 
> 
> ----- Message initial ----
> De : "jdaggett at gate.net" <jdaggett at gate.net>
> À : CoCoList for Color Computer Enthusiasts <coco at maltedmedia.com>
> Envoyé le : jeudi 23 novembre 2006, 10 h 00 min 00 s
> Objet : Re: [Coco] 512KB SRAM upgrade
> 
> 
> Sylvain
> 
> One isue that bothers me and I have to see how the GIME chip does refresh of 
> the dram chips. Right now there appears to be no way to inhibit the writes to the 
> SRAM via the row address during refresh. Not sure if that is going to be an issue 
> but first impressions says it will. 
> 
> I am not sure but I believe the GIME does refresh every horizontal blanking 
> period. I don't have a oscope to setup to measure when the GIME does refresh 
> right now. 
> 
> Everything looks good if and only if you are locked into using 256Kx16 SRAM. I 
> would stay away from LS TTL logic as propogation time could be an issue. Fast 
> Schotky logic would be prefered or as you mentioned doing it in a CPLD. 
>   
> 
> 
> james
> 
> 
> 
> On 22 Nov 2006 at 6:11, Sylvain Rousseau wrote:
> 
> > Hello,
> > 
> > I just finished the design for a 512KB sram upgrade for Coco3.  I have only one Coco3 so I'm afraid to try it in it until I got a spare Coco3 or a spare Gime chip.
> > 
> > If it works well, I want to make the design public.  I can give the design to Mary to put on the Coco Nutz E-zine.
> > 
> > If someone can help me to get a spare Coco3 or a spare Gime chip, please let me know.
> > 
> > P.S. I already have a spare MC68B09EP.
> > 
> > Regards,
> > 
> > Sylvain
> > Quebec
> > Canada
> > 
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