[Coco] Re : 512KB SRAM upgrade

[Mike Pepe]

jdaggett at gate.net wrote:
> Sylvain
> 
> I seriously doubt that the WE0 and WE1 lines remain high suring refresh. In order 
> to do a refresh the row address is placed on the DRAM address lines and then the 
> RAS and WE lines are pulled low. 
> 
> james
> 

Refresh cycles are reads, not writes. Just google and download any 
4164/41256/etc datasheet and check the refresh timing diagrams.

The refresh cycles would be pointless but probably not dangerous.

-Mike