[Coco] MC4517 DRAM questions

[richardcavell at mail.com]

I’ve found a datasheet here for the MC4517 DRAM chip: https://orchidsound.com/mcm4517p12-dram-16-384-bit-16k-x-1-120ns-pdip-16-motorola/

I wonder if I’m reading the datasheet correctly.

1. Is it correct for me to consider that the 7 bit row and 7 bit column addresses could be concatenated into a 14 bit address?
2. Since the chip provides only 1 bit of memory per access, would it be typical to arrange 8 of them in parallel?
3. The datasheet says that it dissipates 14 mW (Standby). What exactly does standby refer to?
4. It has 3-state data output. Does this mean that the default output is high-impedance? When does it produce this output?
5. It has early-write common I/O output capability. What does this mean?
6. The refresh is said to be 64K compatible. I don’t understand what this means.
7. Does it have to be refreshed every 2 milliseconds?
8. It has a hidden /RAS only refresh capability. What does “hidden” mean?