[Coco] 6809 FPGA

[Zippster]

There shouldn’t be any problem DRIVING 5v TTL with 3.3v TTL as you’re well above VIH (by .4v) with 3.3v TTL’s VOH.
I’ve done it plenty of times using CPLDs.

However, you should move to a 3.3v standard for the RAM as 5v TTL is too high for the I/O pins on the FPGA.
Per Altera’s documentation, 3.6v is the maximum input voltage on all Cyclone IV I/O pins.  More than this starts to degrade
the service lifetime of the part.  You can get away with a few tenths of a volt, as part lifetime should still be somewhere
north of 10 years (50% duty cycle IIRC), but 5v is definitely too much.

- Ed


> On Sep 10, 2015, at 10:55 PM, Dave Philipsen <dave at davebiz.com> wrote:
> 
> Oh, and the 3.3v levels are actually TTL.  They're just a low-voltage version of standard 5v TTL.  Some 5v stuff will actually work with 3.3v signals apparently but you probably would get into trouble driving any 3.3v (LVTTL) with 5v signals.
> 
> Personally I would recommend the AS6C4008-55PCN <https://www.mouser.com/Search/ProductDetail.aspx?R=AS6C4008-55PCNvirtualkey56240000virtualkey913-AS6C4008-55PCN>  SRAM. It's 512K, 3.3v - 5v tolerant, and only costs around $4.50.
> 
> Dave Philipsen
> 
> On 9/10/2015 10:36 PM, Dave Philipsen wrote:
>> 
>> 
>> On 9/10/2015 10:12 PM, Bill Nobel wrote:
>>> Hey all,  I (as some of you know) have been trying to get Grant Searles project running on a DE0 Nano. I have made some good advancements (Many, many thanks greatly to Roger Taylor and Dave Philipsen).
>>> 
>>> But I need a little help again.  I took Rogers suggestion of updating my Quartus ii software to 15.0 and things did dramatically change.  I now have a flashing cursor in the top left corner (which should be there upon init of the VGA circuit).  I do have what seems like a little sync noise on the background (nothing serious).  I could post a pic, but I don’t want to clog the list.  This is all I get once I program the DE0 with Grants code.
>>> 
>>> I think there is a problem with my selection of the external RAM chip (and or the pins I chose to drive it, it is all on GPIO-0) I am using a Hitachi 628128 128k SRAM (only using 64k).  I am personally thinking, looking at the data sheet for the RAM, that it might not handle 3.3v CMOS levels good enough.  Am I correct?
>> 
>> Yep, that's a 5v SRAM.  And my guess is you need a 3.3v SRAM.  I am not positive on what the DE0 does for I/O but if it's like the DE1 then it's 3.3v.
>> 
>> 
>>> 
>>> Also, I do think something is wrong in the ROM code, it does compile, but I see in the reports, that there is a rollover in the intel HEX code and I don’t see any LU’s allocated for it in the compile reports.  I get a total of 44 warnings (most are for pin assignments I have not assigned yet).
>> 
>> Not sure what you mean by rollover.
>> 
>>> 
>>> I also see a discrepancy on the pin planner versus the assignment editor, The pins are duplicated in the assignment editor, one set stating my location assignments, the other just stating location.  Is this normal?
>> 
>> You could have some pins duplicated in the assignment editor if one line assigns the signal to a pin and another line defines something else about the pin like whether it has a weak pull-up resistor attached to it for example.
>> 
>>> Bill Nobel
>>> 
>>> 
>> 
>> Dave Philipsen
>> 
>> 
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