[Coco] CoCo 1/2 VDG & SAM interaction.

[Zippster]

Hi Phil,

My understanding from the CoCo 1/2 schematics is that the way it’s arranged the 6847 controls when the bus is
free for the rest of the system.  *FS is tied to *MS on the 6847 and CB1 on the PIA.  

When *FS goes low, *MS is asserted, driving the MC6847’s connections to the address bus into Hi-z.  
At the same time, CB1 on the PIA (an input) is also driven low.  I assume it’s through this that the SAM knows the 
address bus is free.

So, the system doesn’t know if the 6847 started on the rise or fall of the clock.

- Ed


> On May 31, 2015, at 1:00 PM, Phill Harvey-Smith <afra at ramoth.org.uk> wrote:
> 
> Hi all,
> 
> On the VDG data sheet in the sections under the timing for the memory accesses it says that "The VDG may power up using the rising or the falling edge of the clock".
> 
> Now presumably the SAM needs to detect which edge of the clock the the VDG is using so that it can maintain the correct RAM timing and work the data hold latch for the VDG.
> 
> So does anyone know exactly how the synchronization takes place, I would guess that it maybe compares the first transition of DA0 after the end of HS with the phase of the video clock (which it of course generates) to determine if it changed on a rising or falling edge.
> 
> Cheers.
> 
> Phill.
> 
> -- 
> Phill Harvey-Smith, Programmer, Hardware hacker, and general eccentric !
> 
> "You can twist perceptions, but reality won't budge" -- Rush.
> 
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