[Coco] CoCo 1/2 VDG & SAM interaction.

[Phill Harvey-Smith]

Hi all,

On the VDG data sheet in the sections under the timing for the memory 
accesses it says that "The VDG may power up using the rising or the 
falling edge of the clock".

Now presumably the SAM needs to detect which edge of the clock the the 
VDG is using so that it can maintain the correct RAM timing and work the 
data hold latch for the VDG.

So does anyone know exactly how the synchronization takes place, I would 
guess that it maybe compares the first transition of DA0 after the end 
of HS with the phase of the video clock (which it of course generates) 
to determine if it changed on a rising or falling edge.

Cheers.

Phill.

-- 
Phill Harvey-Smith, Programmer, Hardware hacker, and general eccentric !

"You can twist perceptions, but reality won't budge" -- Rush.