[Coco] Altera DE1 - CoCo3FPGA suggestions

[tim at franklinlabs.com]

On February 20, 2014 at 10:57 PM Mark McDougall <msmcdoug at iinet.net.au> wrote:
> On 21/02/2014 11:05 AM, tim at franklinlabs.com wrote:
>
> > Also, and I know this is a BIG also, release the source. I've been working
> > with
> > the DE-1 for about 1 1/2 years now and know it quite well. I would like to
> > have
> > at some custome mods to his code like implementing the SDRAM instead of the
> > SRAM
> > as it's base. This would give the CoCo(4) as full 8 meg of memory for all
> > sorts
> > of game than Nick can write! :o)
>
> This may or may not be possible, depending on the latency of the SDRAM on
> the DE1. I've never sat down to work out what sort of effective clock rate
> you could achieve accessing it randomly, but with the Coco interleaving
> CPU and video accesses, it might be a tall order, especially if you want
> to speed up your CPU!?! And to have any sort of hope of meeting timing
> requirements, the SDRAM controller logic would have to be in the same
> clock domain as the Coco accessing it - another logistic problem,
> especially if you plan on modifying an existing design!

I've been working on my own SOC which is, at this point, a non CoCo 6809 based
controller. I've been blocked from moving forward on this very issue. I have a
solution in my mind. I need to find the time to test it. I plan on using the
SRAM for the video and the DRAM for the CPU. The CPU to Video data transfer fix
still needs some work and testing but it involves a FPGA RAM FIFO controller.

>
> Platforms like Minimig, for example, don't have this issue with SDRAM
> because of the asynchronous 68K bus.
>
> I know MikeJ of FPGAARCADE.COM has written an 'SRAM wrapper' for the DRAM
> memory on his Replay FPGA board. The access time escapes me atm though...

That's a new resource for me. I'm going to check it out. Thanks!!!

> Regards,
>
> --
> | Mark McDougall | "Electrical Engineers do it
> | <http://members.iinet.net.au/~msmcdoug> | with less resistance!"
>
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