[Coco] Altera DE1 - CoCo3FPGA suggestions

[Mark McDougall]

On 21/02/2014 11:05 AM, tim at franklinlabs.com wrote:

> Also, and I know this is a BIG also, release the source. I've been working with
> the DE-1 for about 1 1/2 years now and know it quite well. I would like to have
> at some custome mods to his code like implementing the SDRAM instead of the SRAM
> as it's base. This would give the CoCo(4) as full 8 meg of memory for all sorts
> of game than Nick can write! :o)

This may or may not be possible, depending on the latency of the SDRAM on
the DE1. I've never sat down to work out what sort of effective clock rate
you could achieve accessing it randomly, but with the Coco interleaving
CPU and video accesses, it might be a tall order, especially if you want
to speed up your CPU!?! And to have any sort of hope of meeting timing
requirements, the SDRAM controller logic would have to be in the same
clock domain as the Coco accessing it - another logistic problem,
especially if you plan on modifying an existing design!

Platforms like Minimig, for example, don't have this issue with SDRAM
because of the asynchronous 68K bus.

I know MikeJ of FPGAARCADE.COM has written an 'SRAM wrapper' for the DRAM
memory on his Replay FPGA board. The access time escapes me atm though...

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"