[Coco] 6809's CWAI & SYNC ops

[john dumas]

On 3/4/2013 10:15 AM, Boisy G. Pitre wrote:
> This question is very close to the work I did on my thesis, "Compiler-Assisted Energy Reduction for Microprocessors: Measurement and Analysis" back in 2010. For that work, I measured the power dissipation of the 6309 (not the 6809) using various instructions.
>
> I pulled out my thesis book and looked it up. On average, CWAI (18 cycles) consumed 6.771 milliwatts of power on a 6309 running at 1.78MHz. In relation to that, NOP consumed 8.758 milliwatts, LDQ #$0456B56A consumed 11.148 milliwatts, and the DIVQ instruction consume 14.104 milliwatts.
>
> So for the 6309, there appears to be some power savings using CWAI, but as far as the chip running cooler as a result, I don't know, I didn't take temperature measurements.
I am not knowledgeable about the 6309, but it certainly seems reasonable 
that you could see about 2:1 change
in power consumption from  a very active instruction to one where 
portions of the chip are not switching (as I assume is
the case with CWAI), What I was alluding to is the great difference 
between CMOS and Depletion Load NMOS  when
parts  - or all - of the chip stops switching. When CMOS goes static, 
the power dissipation is primarily "leakage" - microwatts
in many cases. When stopped, there is no DC path from VDD to GND,,,,,
NMOS on the other hand always has a DC path from VDD to GND in many of 
the gates, maybe 1/2. Thus, milliwatts
of power dissipation whether running or not.......

Of course, if the ROM is implemented as dynamic logic, as was often 
done, you can get a good bit of power
savings by not fetching instructions while you are stopped. Still 
nowhere near the savings of CMOS from active
to inactive states.


cheers,
johnd

>
> On Mar 4, 2013, at 9:20 AM, john dumas <JohnDumas at austin.rr.com> wrote:
>
>> On 3/4/2013 8:39 AM, Brett Gordon wrote:
>>> Here's a question:
>>>
>>> Does the 6809 or 6309 operate any cooler during the duration of a CWAI
>>> or SYNC op ?   Has anyone done any testing?
>> For the 6809(E), probably not.
>> For CMOS power dissipation is pretty much a direct function of
>> frequency - charging/discharging of parasitic capacitance and the
>> DC current that results when the P and N channel xistors are both
>> on during a logic level change.
>>
>> The situation is different for depletion load NMOS (6809). In that case
>> current ALWAYS flows thru a gate when it's output is at ground. One can
>> assume that maybe 1/2 the gates will always be at that level at any one time.
>> The current is set by the W/L (resistance) of the load xistor and swamps out
>> the charge/discharge current of the parasitic capacitance on the node.....
>>
>> Unless Bryant took some special care in the electrical design to "turn off"
>> sections of the logic during the wait and sync, you should see little difference
>> in power dissipation. [During the design phase, I never heard any discussion
>> from Terry or Bryant about such a power saving feature. Not saying it didn't
>> happen, but I would think they would have bragged - especially Terry! - about
>> their innovation, if it existed.......]
>>
>> FWIW,
>> johnd
>>
>>
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