[Coco] 6809's CWAI & SYNC ops

[john dumas]

On 3/4/2013 8:39 AM, Brett Gordon wrote:
> Here's a question:
>
> Does the 6809 or 6309 operate any cooler during the duration of a CWAI
> or SYNC op ?   Has anyone done any testing?
For the 6809(E), probably not.
For CMOS power dissipation is pretty much a direct function of
frequency - charging/discharging of parasitic capacitance and the
DC current that results when the P and N channel xistors are both
on during a logic level change.

The situation is different for depletion load NMOS (6809). In that case
current ALWAYS flows thru a gate when it's output is at ground. One can
assume that maybe 1/2 the gates will always be at that level at any one 
time.
The current is set by the W/L (resistance) of the load xistor and swamps out
the charge/discharge current of the parasitic capacitance on the node.....

Unless Bryant took some special care in the electrical design to "turn off"
sections of the logic during the wait and sync, you should see little 
difference
in power dissipation. [During the design phase, I never heard any discussion
from Terry or Bryant about such a power saving feature. Not saying it didn't
happen, but I would think they would have bragged - especially Terry! - 
about
their innovation, if it existed.......]

FWIW,
johnd