Proposed:
=========
OPCODE UPPER BYTE
=================
single/dual accumulator operand
======================= =======
0 single 0 0 0 single op op3 op2 op1 op0 abs/idx dir/ind
ix1 ix0 Register Offset
abs/idx dir/ind
Addr Mode Register
0000 NEG
0001 OIM *
0010 AIM *
0011 COM
0100 LSR
0101 EIM *
0110 ROR
0111 ASR
1000 LSL
1001 ROL
1010 DEC
1011 TIM *
1100 INC
1101 TST
1110 ???
1111 CLR
0 0 0 1 inherent stack op3 op2 op1 op0
0000 RTI
0001 SWI
0010 SWI2
0011 SWI3
0100 RTS
0101 NOP
0110 SYNC
0111 ???
1000 ???
1001 ORCC #<CC mask>
1010 ANDCC #<CC mask>
1011 CWAI #<CC mask>
1100 ???
1101 ???
1110 ???
1111 ???
0 0 1 0 jmp cond cc3 cc2 cc1 cc0 abs/idx dir/ind
ix1 ix0 Register Offset
abs/idx dir/ind
Addr Mode Register
0000 JPA /JMP/BRA/LBRA
0001 JPN /BRN/LBRN
0010 JPHI/BHI/LBHI
0011 JPLS/BLS/LBLS
0100 JPHS/BHS/LBHS
0101 JPLO/BLO/LBLO
0110 JPNE/BNE/LBNE
0111 JPEQ/BEQ/LBEQ
1000 JPVC/BVC/LBVC
1001 JPVS/BVS/LBVS
1010 JPPL/BPL/LBPL
1011 JPMI/BMI/LBMI
1100 JPGE/BGE/LBGE
1101 JPLT/BLT/LBLT
1110 JPGT/BGT/LBGT
1111 JPLE/BLE/LBLE
* Bcc & LBcc are subsets of the addressing mode
0 0 1 1 stack 00 PSH 00 X PC US IY IX DP AW AD
CC *** note no separate A & B & E & F
01 PUL 01 Y PC US IY IX DP AW AD
CC *** stack should be word aligned
10 PSH 10 U *** alteratively
have separate PUSH/PULL for D and W
11 PUL 11 S *** A/E and/or B/F
would be saved in the high & low bytes
0 1 0 0
0000 BAND *
0001 BIAND *
0010 BOR *
0011 BIOR *
0100 BEOR *
0101 BIEOR *
0110 LDBT
0111 STBT *
1000 TFM R+,R+ *
1001 TFM R-,R- *
1010 TFM R+,R *
1011 TFM R ,R+ *
1100 BITMD *
1101 LDMD *
1110 ???
1111 ???
0 1 0 1
0000 SEXB/SEX
0001 SEXF **
0010 SEQW *
0011 ???
0100 DAA
0101 DAB **
0110 DAE **
0111 DAF **
1000 DAD **
1001 DAW **
1010 DAQ **
1011 MULDW
1100 MULAB/MUL
1101 MULEF
1110 EXG <reg pair>
1111 TFR <reg pair>
0 1 1 0 jsr cond cc3 cc2 cc1 cc0 abs/idx dir/ind
ix1 ix0 Register Offset
abs/idx dir/ind Addr Mode Register
0000 JSA/JSR/BSR/LBSR
0001 JSN **
0010 JSHI **
0011 JSLS **
0100 JSHS **
0101 JSLO **
0110 JSNE **
0111 JSEQ **
1000 JSVC **
1001 JSVS **
1010 JSPL **
1011 JSMI **
1100 JSGE **
1101 JSLT **
1110 JSGT **
1111 JSLE **
* BSR, LBSR & JSR are just Always (subsets of the addressing mode)
0 1 1 1 Effective Addr op3 op2 op1 op0 abs/idx dir/ind
ix1 ix0 Register Offset
abs/idx dir/ind Addr Mode Register
00 AEA 00 X ** Add
01 CEA 01 Y ** Compare
10 LEA 10 U Load
11 ??? 11 S ** ???
1 dual op Accumulator op3 op2 op1 op0
========= =========== ===============
1 dual op 0 0 0 A 0000 SUB
0 0 1 B 0001 CMP
0 1 0 E 0010 SBC
0 1 1 F 0011 ???
1 0 0 D 0100 AND
1 0 1 W 0101 BIT
1 1 0 Q 0110 LD
0111 ST
1000 EOR
1001 ADC
1010 OR
1011 ADD
1100 MUL
1101 DIV
1110 ???
1111 ???
1 dual op 1 1 1 long index 00 AD 00 X abs/idx dir/ind
ix1 ix0 Register Offset
01 CP 01 Y abs/idx dir/ind
Addr Mode Register
10 LD 10 U
11 ST 11 S
ADDRESSING MODE LOWER BYTE
==========================
abs/idx dir/ind Addr Mode Register
======= ======= ========= ========
0 abs 0 direct 0 0 acc 0 0 b1 b0 byte acc A/B/E/F (unsigned)
1 indirect 0 1 0 W word acc D/W (unsigned)
0 1 1 0 long acc Q
0 1 1 1 zero,W (DP + ?)
1 0 0 0 word,W * (DP +
signed ?)
1 0 0 1 long,W *
1 0 1 0 ,W+ byte incr **
1 0 1 1 ,-W byte decr **
1 1 0 0 ,W++ word incr *
1 1 0 1 ,--W word decr *
1 1 1 0 ,W++++ long incr **
1 1 1 1 ,----W long decr **
0 1 imm 0 0 ? ? byte imm (unsigned)
0 1 0 ? word imm (unsigned)
0 1 1 0 long imm
0 1 1 1 zero,D ** (DP + ?)
1 0 0 0 word,D ** (DP +
signed ?)
1 0 0 1 long,D **
1 0 1 0 ,D+ byte incr **
1 0 1 1 ,-D byte decr **
1 1 0 0 ,D++ word incr **
1 1 0 1 ,--D word decr **
1 1 1 0 ,D++++ long incr **
1 1 1 1 ,----D long decr **
1 0 abs 0 0 ? ? byte abs (DP +
unsigned)
0 1 0 ? word abs (DP +
unsigned)
0 1 1 0 long abs
0 1 1 1 zero,Q **
1 0 0 0 word,Q ** (signed ?)
1 0 0 1 long,Q **
1 0 1 0 ,Q+ byte incr **
1 0 1 1 ,-Q byte decr **
1 1 0 0 ,Q++ word incr *
1 1 0 1 ,--Q word decr *
1 1 1 0 ,Q++++ long incr **
1 1 1 1 ,----Q long decr **
1 1 rel 0 0 ? ? byte rel A/B/E/F,PCR (signed)
0 1 0 ? word rel D/W,PCR (signed)
0 1 1 0 long rel Q,PCR
0 1 1 1 zero,PCR **
1 0 0 0 word,PCR ** (signed)
1 0 0 1 long,PCR **
1 0 1 0 ,?+ byte incr **
1 0 1 1 ,-? byte decr **
1 1 0 0 ,?++ word incr *
1 1 0 1 ,--? word decr *
1 1 1 0 ,?++++ long incr **
1 1 1 1 ,----? long decr **
abs/idx dir/ind ix1 ix0 Register Offset
======= ======= ======= ===============
1 idx 0 direct 0 0 X 0 0 b1 b2 byte offset A/B/E/F (signed)
1 indirect 0 1 Y 0 1 0 w word offset D/W (signed)
1 0 U 0 1 1 0 long offset Q
1 1 S 0 1 1 1 zero offset
1 0 0 0 word offset (signed)
1 0 0 1 long offset
1 0 1 0 ,X+ byte incr
1 0 1 1 ,-X byte decr
1 1 0 0 ,X++ word incr
1 1 0 1 ,--X word decr
1 1 1 0 ,X++++ long incr **
1 1 1 1 ,----X long decr **
<reg pair>
0000 A 8 bit
0001 B
0010 E
0011 F
0100 D 16 bit
0101 W
0110 DP
0111 CC
1000 X 32 bit
1001 Y
1010 U
1011 S
1100 Q
1101 V
1110 MD
1111 PC
* 6309 extensions
** New extensions
--
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