[Coco] Learning CPU Architecture and Digital Design

Sun Feb 17 09:14:00 EST 2013

I tried sending an email with a proposed format of a 16 bit opcode map 
but it was too long.
It's awaiting moderators approval.
I've shown Arron Wolfe and William Astle the opcode map a while back.
Most modern CPUs have a pipelined RISC architecture and have a large 
register set.
A 16 bit 6309 has 4 x 8 bit accumulators or 2 x 16 bit accumulators or 1 
x 32 bit accumulator and 4 x 32 bit index registers / stack pointers. 
It's not very easy to implement a large number of registers with the 
6x09 instruction set.

On 18/02/2013 1:05 AM, John Kent wrote:
> There was a course on RISC CPU design on coursera.org.
> They recommended using the yext book:
> Computer Architecture, Fifth Edition: A Quantitative Approach 
> <http://www.amazon.com/gp/r.html?R=117IPCRXL0ET6&C=263FFA4JMHQGQ&H=ZT5BZBEKMXKCKDCHEHYUM62J3Y4A&T=C&U=http%3A%2F%2Fwww.amazon.com%2Freview%2Fcreate-review%2Fref%3Dpe_6680_26660520_cm_cr_ec_add_1_h_c26660520%3Fie%3DUTF8%26asin%3D012383872X%26channel%3Dec_trd_c%26customerID%3DA12L6YIHR9PZQ9%26nodeID%3D>
> (The Morgan Kaufmann Series in Computer Architecture and Design) 
> <http://www.amazon.com/gp/r.html?R=117IPCRXL0ET6&C=263FFA4JMHQGQ&H=ZT5BZBEKMXKCKDCHEHYUM62J3Y4A&T=C&U=http%3A%2F%2Fwww.amazon.com%2Freview%2Fcreate-review%2Fref%3Dpe_6680_26660520_cm_cr_ec_add_1_h_c26660520%3Fie%3DUTF8%26asin%3D012383872X%26channel%3Dec_trd_c%26customerID%3DA12L6YIHR9PZQ9%26nodeID%3D>
> by John L. Hennessy
>
> http://news.stanford.edu/news/2011/december/hennessy-ieee-honor-120111.html
>
> I've made a couple of versions of the 6809 core.
>
> CPU09L is the 8 bit version which has the FIRQ interrupt fixed up.
>
> You know about that Mark,
>
> CPU1609 was an attempt at making the 6809 scaleable.
> It had generic definitions (arguments to the CPU core) for defining 
> the data bus and address bus width.
> It could be implemented as an 8 bit data 16 bit address / 12 bit data 
> 24 bit address / 16 bit data 32 bit address CPU.
> The opcode bytes were still only 8 bit but occupied only part of the 
> 16 bit word.
> It meant that you could use the wider data bus to implement longer 
> addresses.
> There is a problem though.
> The A & B accumulators have to be half the width of the index registers.
> Also you need additional half carry flags, 2 for 12 bit data width, 3 
> for 16 bit data width as the half carries are used for nybble 
> adjustment in the DAA instruction.
>
> I was looking at re-arranging the 6809 instructions so that they 
> fitted in a 16 bit word.
>
> The 6309 has E&F 8 bit accumulators, which combine to make a 16 bit W 
> accumulator  and the W accumulator can be appended to the D 
> accumulator to make a 32 bit Q accumulator.
>
> Here are some notes I made a while back.
>
> ---------------------------------------------------------------------------------------------------------------------------------------------------------------
>
> While looking at the 6309 instruction set, trying to work out what 
> needed to be implemented, I was pondering how to implement a 32 bit 
> version of the 6809/6309.
>
> A lot of low cost FPGA boards such as the DE1 board use 16 bit wide 
> memory, so I was wondering how I could remap the 6809/6309 to make 
> best use of the 16 bit bus.
>
> Many of the 6809 instruction such as the dual operand indexed 
> instructions, could be regarded as 16 bit instructions (2 consecutive 
> bytes). I wanted to get away from using the Page 2 and Page 3 
> pre-bytes so that most of the instructions were mapped into 16 bits. 
> What I did was eliminate the 5 bit offset indexed addressing mode 
> which gave me a spare bit in the indexed addressing byte which I used 
> to map between indexed addressing using the X, Y, U & S registers, and 
> immediate, absolute (extended) and accumulator register addressing.
>
> The proposed design does not have a direct page register. (**** It 
> could) Direct addressing refers to extended addressing as opposed to 
> indirect addressing. i.e indirect mode loads the address from the 
> effective address and uses that for fetching data.
>
> Using the extra addressing byte for register, immediate, and absolute 
> (extended) addressing modes, meant that I had spare bits in the opcode 
> byte that I could use to address the D, E, F, W & Q accumulators. The 
> A, B, E & F accumulators would be 8 bit, the D & W accumulators and DP 
> and CC registers would be 16 bit, and the X, Y, U, S, PC, Q and V (?) 
> registers would be 32 bit.
>
> By having the instructions similar to the 6809, it makes translation 
> of the code easier, however you still have problems with the data 
> alignment and the introduction of 32 bit registers. The X, Y, U, S & 
> PC are no longer the same size as the D & W registers, so it would not 
> be a direct conversion of the code from 6809/6309 assembly source code 
> to the 32 bit version.
>
>
>
> On 17/02/2013 10:35 PM, Mark McDougall wrote:
>> On 17/02/2013 8:30 PM, Kip Koon wrote:
>>
>>> because there are two versions of the 6x09
>>> processor core in existence ready to burn into an FPGA chip.
>>
>> I only know of one version, John Kent's CPU09, which is the core that 
>> Gary Becker is using in his Coco3FPGA project.
>>
>> If you say there's another one, I'd be *very* interested, but I 
>> suspect you're mistaken!?! Hoping not though! :)
>>
>>> I'd like to expand the
>>> 6x09 core (not sure which one to pick yet) into a core with a 24-bit 
>>> address
>>> bus and keep the same 8-bit data bus while at the same time 
>>> preserving the
>>> complete instruction set, if possible.  Has anyone else ever had 
>>> this idea?
>>
>> IIRC John himself was looking at enhancing his CPU09 core, though I 
>> can't recall the exact details of what he was planning. I'm guessing 
>> you're looking at some sort of 'segment' (for lack of a better word) 
>> register(s)?!?
>>
>>> I'd also like to study this subject in
>>> detail.  In order to facilitate my studies, which book(s) would you all
>>> suggest I look into getting?  Thank you all for your help.
>>
>> There was a book on CPU design in VHDL but I can't recall the title 
>> (never used it). A quick google search brought up a PDF from 
>> opencores on the subject, for example.
>>
>> I think if you have some sort of grounding in CPU architecture you 
>> best bet would be to dive in and study the CPU09 core itself. I've 
>> personally studied a few of the cores (6502 & Z80 primarily) and 
>> briefly perused John CPU09 core (to track down an issue) and it's not 
>> that difficult to grasp how they work if you spend enough time with 
>> them. Of course, you still need a grounding in CPU architecture first.
>>
>> Regards,
>>
>
> -- 
> http://www.johnkent.com.au
> http://members.optusnet.com.au/jekent

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