[Coco] CoCo bus interface project

[Darren A]

On Wed, Apr 17, 2013 at 6:45 PM, Matthew D Stock  wrote:
> Thanks everyone for your support on this project, it's been a learning
> experience.  If I lived closer to Chicago, I'd be tempted to go to the
> 'fest.
>
> I have a question for those of you on the hardware side...  I'm having some
> issues with ROM images that are greater than the usual 8k ROM segment.  In
> particular, I'm trying to understand how the 32K ROM PAKs were wired, not
> having one myself.  My assumption was that the 32K ROM was mapped to the
> upper half of the address space, and that on boot the ROM startup code in
> the $C000 segment would disable the built-in BASIC ROMs.  What I don't know
> is if the ROM cartridge needs to help, like also asserting SLENB.  Or if CTS
> is asserted for the entire upper half of memory when the BASIC ROM is
> disabled, or if the ROM board needs to decode the addressing, etc.
>
> I've looked in many of the doc caches, and I can't seem to find anything
> like a developer's guide to ROM PAKs.  Before I keep going with trial and
> error, can anyone shed some light?
> Thanks,
>   -Matt
>
--

The CoCo 3 has a 32K external ROM mode that is activated by some bits
in the GIME.  This mode activates CTS assertions for the upper 32K of
the address space.

The CoCo 1 and 2 have no such mode.  For those you would need to
decode the addresses yourself and assert SLENB to prevent the internal
ROMs from being selected.

Some commercial ROM Paks included their own custom circuit for bank switching.

Darren