[Coco] Xilinx ISE Assigning Signals to Specific Pins

[John Kent]

Yes,

Setting up the UCF file is rather tedious, but once it's done, you 
generally don't have to change it, unless you add some more hardware.
You basically map the signal names on the entity interface to the pin 
numbers, and you can also specify the interface characteristics of the pins.
If you don't specify a UCF file, the Xilinx software will auto assign 
pins, based on what the closest pin is to the design.
Normally you want pins assigned pins particular positions to match the 
hardware you have the FPGA wired up to.
It's also important that you don't assign output pins on the FPGA to 
output pins form the chips that the FPGA is wired to.
Otherwise you may have two outputs driving each other.
I'm not sure if Kip is designing with an FPGA or CPLD or if he is using 
a development board with peripherals already on it.

John.

On 18/10/2012 12:54 PM, jdaggett at gate.net wrote:
> Mark
>
> i agree that assigning any UCF file on a very large pinout design is tedious and easily frought
> with potential mistakes. I am also aware that preassigning pins in the initial start can be a
> problem due to routing delays.
>
> It is at best a no win situation at times.
>
> james
>
>

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