[Coco] Xilinx ISE Assigning Signals to Specific Pins

[jdaggett at gate.net]

Mark 

i agree that assigning any UCF file on a very large pinout design is tedious and easily frought 
with potential mistakes. I am also aware that preassigning pins in the initial start can be a 
problem due to routing delays. 

It is at best a no win situation at times.

james

On 18 Oct 2012 at 9:04, Mark McDougall wrote:

> On 18/10/2012 1:20 AM, jdaggett at gate.net wrote:
> 
> > Doesn't Floor Planner alllows a graphical assignment of pins? I have
> > never used it though it is there as a part of Webpack 10.1 which I am
> > still using.
> 
> Altera is my bread-and-butter, only used Xilinx a handful of times, and then 
> I used UCF files. No doubt you can do it graphically, as you can (or choose 
> not to) in Altera, but my point was, it's still painful! :(
> 
> Regards,
> 
> -- 
> |              Mark McDougall                | "Electrical Engineers do it
> |  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"
> 
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