[Coco] CoCo 1&2 clock cycle events (CPU, SAM, VDG interaction with RAM)

[Darren A]

On 5/21/10, Fedor Steeman wrote:
> Hi all,
>
> Looking in the Technical Ref Manual, studying the diagrams, and several
> other sources on the internet, I am trying to understand exactly the
> sequences of events during a CoCo 1/2's clock cycles. As I am not an
> electronics buff, this is not an easy task for me. I just wanted to know in
> what order, CPU, and VDG interact with RAM, as mediated by the clocking
> signals provided by the SAM.
>

---

This is my understanding.  Someone please correct me if I'm wrong:

The CPU presents a stable address from the rising edge of Q to the
falling edge of E.  The CPU's data window is in the latter portion of
E High. Data is latched by the CPU on the falling edge of E.

The SAM is responsible for addressing RAM using either the CPU address
or its own internal video offset counter.  It (roughly) presents the
CPU address after E goes High and the VDG address after E goes Low.
The VDG reads RAM during the latter portion of E Low.

Darren