[Coco] CoCo 1&2 clock cycle events (CPU, SAM, VDG interaction with RAM)

[Fedor Steeman]

Damn! Have been messing a bit too much around in the list. What I meant was:


        E-low & Q-low: VDG reads data byte
        E-low & Q-high: CPU sets RAM address
        E-high & Q-high: CPU reads/writes RAM byte
        E-high & Q-low: SAM sets RAM address for VDG

/Fedor

On 21 May 2010 14:09, Fedor Steeman <petrander at gmail.com> wrote:

> Hi all,
>
> Looking in the Technical Ref Manual, studying the diagrams, and several
> other sources on the internet, I am trying to understand exactly the
> sequences of events during a CoCo 1/2's clock cycles. As I am not an
> electronics buff, this is not an easy task for me. I just wanted to know in
> what order, CPU, and VDG interact with RAM, as mediated by the clocking
> signals provided by the SAM.
>
> This is what I pieced together so far:
>
>  - E-low & Q-low: VDG reads data byte
>  - E-low & Q-high: CPU sets RAM address
>  - E-high & Q-low: CPU reads/writes RAM byte
>  - E-low & Q-low: SAM sets RAM address for VDG
>
> Is this correct? Or how else should this picture look like?
>
> Thanks for any insights!
>
> Cheers,
> Fedor
>
>