[Coco] 6309 Weirdness ??

[Darren A.]

>From:  (John Kowalski)
>Subject: Re: [Coco] 6309 Weirdness ??
>
>Hi Darren,
>
>I haven't checked this yet myself, but I suspect if there is some funny
>stuff going on with the PC value during execution of opcodes that are able
>to affect the PC register, it would likely be the result of the 6309's
>opcode prefetch/optimisation.
>
>It may be that at the time ADDR X,PC is performing the operation on the PC
>register, the CPU may have already prefetched (or may even be concurrently
>prefetching) the first byte of the next opcode and advanced the PC an extra
>byte.
>
>(Potentially, a further bug/glitch may result if the PC is modified *after*
>the CPU had already prefetched the next opcode.  It may execute the already
>prefetched byte but continue subsequent byte reads from the *modified* PC
>value.)
>
>I'm not sure how interrupts might affect this, but there may be potential
>for the PC to act differently in this case if an interrupt is triggered mid
>execution of the ADDR X,PC operation - in that the CPU will not try to
>prefetch the next opcode (therefore not cause the glitch) if it knows it 
>has
>to process the interrupt after this opcode.
>
>Just my 2 cents.  It sounds like a very plausable/possible "glitch" in 6309
>operation.
>
>
-

John,

Your description fits quite nicely with the results I am seeing. It looks 
like the engineers failed to correct for the pre-fetch adjustment in these 
instructions as is done in others (branch-relative and PC indexed).

If you could always assume that an offset of 4 (from the instruction 
address) was being used, then a workaround would be simple. Unfortunately, 
the interrupt issue makes that assumption unreliable. Probably best to avoid 
using the PC register with these instructions unless interrupts are masked.

The question this raises:  Should MESS be updated to emulate the "glitch"?

Darren

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