[Coco] Dynamic RAM Q

Phill Harvey-Smith afra at aurigae.demon.co.uk
Mon Oct 9 16:22:39 EDT 2006

Mike Pepe wrote:
> Phill Harvey-Smith wrote:
> Phill,
> You know, this problem has already been solved.
> In Rainbow magazine there was a project published for a 256k upgrade.
>  The upgrade involved a 74LS785 SAM and 256k memory chips (they need
> 256 column refresh, which the LS785 provides)

Is that available anywhere, I would be interested in seeing that :)
I do have a couple of 785s, one in one of my CoCo2s and a spare just
incase :) I have tested and it works fine in the Dragon also, though as
someone else pointed out, they are pretty R at RE :) (the people who trade
on ebay will get that one :) ).

Though using the SIMM, refresh is not a problem, as the ram chips on the
SIMM have an internal refresh counter, that is clocked by a cycle with 
CAS before RAS, so I reverse CAS & RAS when both /HS and E are low, this
seems to keep the RAM refreshed.

> I don't recall the details but I don't believe there was anything
> more exotic than a mux controlling the A9 line for the 41256 chips.
> Maybe someone has the article handy in their collections and can
> provide us the details.

Yeah that should work, this is what I did for the Dragon Plus
'emulation', which gives an extra 64K, paged in the bottom 32K.

> I do remember the thing was controlled by doing reads of the SAM
> bits.

Humm that's an interesting method, sort of the inverse of how the SAM 
control bits work.


Phill Harvey-Smith, Programmer, Hardware hacker, and general eccentric !

"You can twist perceptions, but reality won't budge" -- Rush.

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