[Coco] FPGA CoCo

[Mark McDougall]

jdaggett at gate.net wrote:

> One issue that I have to be sure that does not bite me is that when the
> address buss to the ram switches properly between CPU cycle and Video
> cycle. ALso to make sure that Video section does not try and read the
> video ram when the CPU is acessing the ram.

Right now I've got 16 system timeslices per cpu clock. I've got some logic 
that brings the 6883/6847 out of reset at the right phase wrt the cpu and 
from then on things happen on a certain timeslice - with roughly the same 
phase relationships as the timing diagram in the coco reference manual.

I'm using SRAM atm so refresh cycles are completely ignored, although I'm 
generating RAS/CAS just for the sake of it. If I do elect to implement the 
full functionality of the 6883 I'll have to fix that up of course.

I haven't had a lot of experience with video signal generation, so last 
night I started on a simple controller hard-coded for 640x480. The idea is 
that I'll have a dual-port line buffer fed by the 6847 at PAL/NTSC 
frequencies and then have my vga controller suck it out the other end, 
handling the scan-doubling. At least that's the initial plan, it may change 
as I become more familiar with video...

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"