[Coco] FPGA CoCo

[jdaggett at gate.net]

Mark

One issue that I have to be sure that does not bite me is that when the address buss 
to the ram switches properly between CPU cycle and Video cycle. ALso to make 
sure that Video section does not try and read the video ram when the CPU is 
acessing the ram. 

Yes the clcok generation circuits or digital clock modules are proprietary between 
FPGA makers. That code is easily modified as well as block ram. Outside that HDL 
code is is somewhat transportable. 

james

On 27 Mar 2006 at 18:19, Mark McDougall wrote:

> jdaggett at gate.net wrote:
> 
> > I am using a Digilent Spartan 2E board and Xilinx Webpack ISE 8.1.  Like
> > the Altera software, Webpack is free. There are some minor advantages of
> > the the Xilinx software over the Altera. The development board has a 300K
> > equivalent gate FPGA on it and is now available for $89 US.
> 
> There's nothing really tied to Altera in my design except for the PLL 
> (generating roughly NTSCx4) and the block ram (easily changed).
> 
> Having said that, I'm not sure there's anything that could easily benefit 
> from another pair of hands. The 6847/6883 go hand-in-hand and is a block of 
> work that can't really be partitioned.
> 
> Seems James has the GIME under control so that takes care of the CoCo 3 as 
> well...
> 
> Regards,
> 
> -- 
> |              Mark McDougall                | "Electrical Engineers do it
> |  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"
> 
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