[Coco] SockMasters' 4mhz circuit.

[Paul T. Barton]

John,

--- John Kowalski <sock at axess.com> wrote:

> At 09:09 AM 26/08/2005 -0700, CoCoList for
> Color Computer Enthusiasts wrote:
> >SockMaster,
> >
> >Just got my CPLD 4mhz to run at stock speed
> >(actually it's both slow & fast).
> >For your program to test speed inprovement,
> >I get 129-138 for the printout at stock speed
> >on a 63b09e non-native mode.
> >
> >Paul - idezilla
> 
> Cool!  By slow & fast, I assume you mean that
> some opcodes take more cycles
> to execute and other take fewer cycles than on
> an actual Motorola 6809 CPU,
> right?
> 
> The 129-138 averages to about 134, and if you
> applied it to double speed
> (1.79Mhz) mode, it would be about 268 -
> coincidentally very similar to the
> result I got with my old "clock doubled" 6809. 
> About 34% faster than a
> standard CoCo or the equivalent of about 2.4Mhz
> CPU performance.
> 
> Which opcodes execute faster and which ones
> slower, by the way?  I'm very
> curious.  Please keep us curious folk informed
> - I'm sure there are a lot of
> people interested in a faster plug-in 6809/6309
> CPU replacement.
> 
>                                          John
> Kowalski (Sock Master)
>                                         
> http://www.axess.com/twilight/sock/

Gee, John, I don't know.
I use AVMA, BA & BS, all three
to mark out "next cycle usage".
So, whatever comes up, gets it.
For now, my 63B09e won't do the 4mhz
but will do the half-speed one.
Since the 28.63636 crystal broke it's
legs off, I've plugged in a 29.0000MHz
xtal for this machine. Maybe this is
a challenge (I don't think so, as
it's really close). I need to dig up
my 63C09e for continued testing.

All of this in a NoCan-8mb version,
where the CPU address and R/W lines
are buffered.

---

I figured out another wiring scheme
inside the CPLD to give 1.5 cycles of
the 28MHz per waveform. They overlap
at 33% which should do the job nicely.
Run the 28MHz through an XOR gate leg
and delay the other XOR leg by a
IN/OUT + inverter pins (out the
package and inverted & back in again).
[I tried to do this all internally,
but the compiler/fitter saw this as
a "challenge" and eliminated the 28MHz
inpout pin, ARGH!]
This effectively doubles the clock edges
to the 4-bit counter. The $FFD9 poke
detector then controls a mux of 28MHz
or 56MHz to the 4-bit counter. re-constructed
wave forms do not suffer, so far. Counter is
reset by Q. AVMA, BA & BS latched by falling
edge of E; the AVMA etc latch is not reset,
just clocks the signals every falling E.
This forces the counter to only run during
the E&Q combined low time, a narrow timing
window indeed.


Paul



		
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