[Coco] Re: GCC: DFLOAT / DIRECT_PAGE

[jdaggett at gate.net]

John

A common method that I have seen in routines for the HC11 and others processors 
is to:

1) shift out the sign bit to a byte of its own. 
2) put the exponent in two bytes for double precision. one byte for single. 
3) the mantissa is adjusted to fill as many bytes as required for the precision.
4) all math is done on the exponent and mantissa separately.

here is a assembly routine to unpack

***************************
*  IEEE FP Double Precison Unpack 
*      for the 6809 
*     by James Daggett
***************************

* IEEE FP Accumalators. Global variables
FPACC0		rmb	8
FPACC1		rmb 	8
FPACC2		rmb 	8

* Internal working FP accumalators. Local variables

FP0Sign	rmb 	1
FP0exp		rmb	2
FP0man	rmb	7
FP1Sign	rmb 	1
FP1exp		rmb	2
FP1man	rmb	7
FP2Sign	rmb 	1
FP2exp		rmb	2
FP2man	rmb	7

*********************************
* UNpack FPACC0 from IEEE format. 
********************************* 
start		ldx	FPACC0
		ldy	FPA0Sign

*****************************
*  ACCB now has the first 8 bytes of the FPACCx
* Sign extend and A will have the value of the sign
* bit which resides in bit 7 of ACCB. 
*****************************
		ldab	0,x
		sex	
		sta	0,y	store sign

****************************
* Now shift the sign bit out of the exponent in B
*  We first load in the first two bytes into D
****************************

		ldd	0,x
		lslb		shift b7 out of A
		rola		and into b0 of A
		std	1,y	store the first exponent

****************************
* Now we process the mantissa
****************************

		ldd	1,x	get the first two  partial bytes 
		anda	$0F	mask out the upper nible
		bsr	rotd4x
		sta	3,y	store the 1st byte of the mant.
		ldd	2,x
		bsr	rotd4x
		sta	4,y	store the 2nd byte
		ldd	3,x
		bsr	rotd4x
		sta	5,y	store the 3rd byte
		ldd	4,x
		bsr	rotd4x
		sta	6,y	store the 4th byte
		ldd	5,x
		bsr	rotd4x
		sta	7,y	store the 5th byte
		ldd	6,x
		bsr	rotd4x
		sta	8,y	store the 6th byte
		stb		store the 7th byte
		rts

*********************************************
*  ROTD4X 
*    rotate D four times.
*********************************************
x		lslb		move b7 of B into the carry
		rola		move the carry into b0 of A 
		lslb
		rola
		lslb
		rola
		lslb
		rola
		rts
 

On 15 Nov 2003 at 19:43, John E. Malmberg wrote:

> Theodore A. Evans wrote:
> <snip>
> Thanks for the research.
> 
> GCC knows about IEEE floats, and it knows two other float types from
> popular pre-IEEE standard that are built into the hardware.
> 
> I do not know how much work it would be to add COCO float type, and
> that 
>   is not something that I will be pursuing from the compiler point of
> view.  Since it is open source, it is fair game for anyone else
> though.
> 
> It looks like to make the compiler happy, I will need to figure out
> how to have the 6809 manipulate a IEEE double presision float.
> 
> 
> One thing I forgot to mention about the direct page, for some Motorola
> processors, GCC uses the direct pages as banks of registers.
> 
> If I can get the direct page stuff implemented the way that I
> envision, I think that everyone will be happy with the result, because
> all usage patterns that I have seen reported here could be coded.
> 
> 
> I am going to look at the Dfloat issue tonight if I get some spare
> time to see if I can find out how to implement it.
> 
> 
> -John
> wb8tyw at qsl.net
> Personal Opinion Only
> 
> 
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