[Coco] Embedded coco

[peak at mail.polarcomm.com]

James
Before you (and everyone else) virtualy smacks me one the 
head. Here is more of the address decoder.
Shortly after I sent you the outline of the decoder it 
occured to me that there are some "problems" with it.

Because each output of the decoder is active at 2 time for 2 
different block sizes we would need some post decoding to 
separate them.
The Y7 output is useable as is because both active times:
8K rom init routine, and 32 byte interrupt and reset vector 
blocks could be in the same rom chip.
When we get to Y6 we could use a 2-input nand gate to combine 
y6 with the output of the FFXX detector to give us an enable 
signal for only the 8k time (CTS enable).

Y5,Y4,and Y3 could just be ignored(not used).

When we get to Y2 we could again use a nand gate and inverter 
to combine Y2 with the FFXX detector to give us only the 32 
Byte signal(SCS).

At Y1 we would use both versions of the post decoder. This 
would give a 32Byte PIA enable as well as an 8k enable at 
$2000(I call this the "James ckt" ha ha).

At Y0 again use both post decoders giving another PIA enable 
and an 8k enable for RAM(the "eric ckt").

Now I do realize that the Y1-8K is an 8k byte block and you 
2716 chip is only 2k. The answer to that is/could be:
1. Use a 2716 and let it ghost to the other 3 2k parts.
2. Use a 2764 8K Eprom Instead.
3. Use additional decoding for only the 2716. An ls139 chip 
with the CPU's lower address lines would do this.
4. Use a lot of ram in this area instead(32k?).
I dont know which you would prefer so I'll leave it up to you.

As to the same situation at Y0 for the ram, as for now I 
would like to place a 6116 2k ram there and just let it ghost 
to the other 6k of this block.

Later in the day I came up with another solution to the 
decoder "problem". Here it is:
Use 2 LS138 equivalent ckts.
One connected to A15-A13 and the other one connected to A4-
A7. This would completely separate the 8 32Byte enables from 
the 8 8K enables. This would also eliminate the address line 
switcher/multiplexer and would eliminate the "post decoders", 
also eliminating any propagation delays that they would cause.
If we do it this way(2 each 138 equiv's) then we need to OR 
gate the Y7 outputs together for the ROM enable. Also we need 
to connect the SLENB cartrige pin to disable both 138's.

I know that this is probably a lot to digest but you are the 
one who said you could probably put it together by new Years 
day. Happy New Year!!
Eric