[Coco] 64K Coco mode and the MC6883

[Sean Conner]

Hello.

  I was recently doing some retro programming for the Coco-2 (using the
xroar emulator) that required me to set it up into the 64K RAM mode.  I had
fun writing what should be the fastest way of doing that [1] but some people
asked some questions about the code and it got me wondering *why* the code
works.

  One question is why we have to toggle the ROM/RAM for each copy?  Why
don't writes to ROM just pass to the underlying RAM?  I wanted to figure out
the answer, so I started by checking out the data sheet for the MC6883 (SAM
chip) [2].  The SAM chip will generate a 3-bit signal, S0-S2, for any given
address, and in the default mode, figure 14 shows the various S values (for
S0-S2 pins) for each segment of memory:

	Address		Read	Write
	-----------------------------
	$0000-7FFF	0	7
	$8000-9FFF	1	1*
	$A000-BFFF	2	2*
	$C000-FFEF	3	3*
	$FF00-FF1f	4	4*
	$FF20-FF3F	5	5*
	$FF40-FF5F	6	6*
	$FF60-FFDF	7	7*
	$FFE0-FFFF	2	2*

	* I'm not sure this is true, as the data sheet doesn't explicitely
	  state so.

The S bits are used as chip selects, as shown by the Color Computer
schematic from the Technical Manual [3].  Also from the SAM data sheet, it's
clear that the locations $FFDE/FFDF toggles the Map Type, and that figure 14
refers to map type of 0 (default configuration).  If we go to Figure 15, we
get a list of S values for each range for Map Type 1 (64K RAM):

	Address		Read	Write
	-----------------------------
	$0000-7FFF	0	7
	$8000-9FFF	0	1
	$A000-BFFF	0	2	***
	$C000-FFEF	0	3
	$FF00-FF1f	4	4
	$FF20-FF3F	5	5
	$FF40-FF5F	6	6
	$FF60-FFDF	7	7	**
	$FFE0-FFFF	2*	2

	* I think this is the case, and the data sheet seems to imply that
	  vectors from $FFF2-FFFF are pulled from $FFB2-FFBF.

	** (From the data sheet) Decode S2, S1, and S0 with an open
	   collector SN74LS156 and 'wire-or' state 7 with state 2 (See
	   Appendix B for suggested decode circuit).

	*** (From the data sheet) To avoid ROM enable during R/-W = LOW, the
	    ROM at S=2 must be gated with R/-W (See Appendix B for suggested
	    decode circuit).

And here is were I start getting confused.  The schematic doesn't show any
circuit that matches Appendix B, and the fact that writes still select the
ROMs appears to me that writes to ROM (in the default mode) *might* still
write through to RAM, although I can't test that as my Coco-2 is currently
in storage, so I can't currently test my hypothesis that you don't need to
switch ROM/RAM when copying ROM to RAM (I don't want to test this with an
emulator as it may not accurately emulate this).  Does anyone on this list
have a 64K Coco-1 or Coco-2 that this could be tested on?

  Thanks for any help in explaining how this works.

  -spc

[1]	https://boston.conman.org/2023/03/13.2
	Upshot: I used puls/pshs to copy the ROMs to RAM, using 6.125 cycles
	per byte per iteration of the loop.

[2]	https://archive.org/details/Motorola_MC6883_Synchronous_Address_Multiplexer_Advance_Sheet_19xx_Motorola

[3]	https://archive.org/details/Color_Computer_Technical_Reference_Manual_1981_Tandy/mode/2up
	This manual matches the one I bought at Radio Shack back in 1985 or
	1986 (don't recall the actual year).