[Coco] Regarding 6800 peripheral ICs

[Jim OKeefe]

When I got to the end of the message I was shocked to see that Jim had
changed his name to Jorge.  Then i thought maybe he has a split
personality.   After scrolling up I realized my mistake,  my bad,  I'm
getting old. It was an interesting read and I learned something I didn't
know. Got me thinking about the 8080 and it's 3 supply voltages,  always
wondered why that was,  now I know,  thanks Jorge or Jim or whatever your
name is ;) See you at Cocofest.

Regards Jim.
Unless my name is Jorge too. I'm confused.

On Wed, Mar 9, 2022, 12:14 AM RETRO Innovations <go4retro at go4retro.com>
wrote:

>  From another mailing list:
>
>
> I assume most people here is familiar with enhanced mode logic that
> predates NMOS depletion mode logic. Enhanced mode logic uses enhanced
> mode transistors only, including for the pullups. In contrast to
> depletion mode pullups, enhanced mode pullups produce a voltage drop at
> the high state. To compensate for this, enhanced mode logic normally
> used multiple power supplies and two separate power rails for the
> pullups, one for the gate and the other for the drain. This was one of
> the main drawbacks of enhanced mode logic.
>
> Some of the latest enhanced mode chips, notably the Motorola 6800, had a
> single power supply. The 6800 has an internal voltage booster.
> Internally still has two separate power rails for the pullups. I assumed
> the main 6800 peripherals, since they also have a single power supply,
> that they use the same technology. But I recently found that I was
> wrong. At least ACIA (MC6850) and the older versions of PIA (MC6820)
> don't have an internal voltage booster. They are still enhanced mode
> logic but with a single power rail for the pullups! I was initially
> quite surprised because I assumed this was, at best, very inefficient,
> but obviously it works fine.
>
> So, these chips are enhanced mode logic, bit with a single power rail
> for the pullups, with both the gate and drain of the pullups tied to
> Vcc.  The only obvious limitation of this technology seems to be
> regarding pass transistors. I cannot find a single pass transistor in
> ACIA layout. This makes sense when you consider that pass transistors
> produce another voltage threshold drop. This would result in two voltage
> drops in a row, and then probably the output of the pass transistor at
> the high level would be too low. Not being able to use pass transistors
> is a severe limitation. Pass transistors are used extensively in
> sequential logic, especially in dynamic cells that is based on the
> capacitance at the input to the pass transistor. There are no dynamic
> cells in ACIA as far as I can see, and there is no non-overlapping clock
> generator as it is typically in most NMOS clocked devices. Synchronous
> logic is implemented with static flip flops instead, and again, without
> any pass transistor. Note that NMOS, and also CMOS, typically do use
> pass transistors also for static logic.
>
> I am curious if somebody else find other chips with enhanced mode logic
> and a single pullup power rail. I would also be interested if somebody
> heard about some paper, documentation, or patent in the subject. ACIA is
> actually patented, but this feature is not described in the patent.
>
> Thanks
>
> jorge
>
>
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