[Coco] GIME DRAM address mappings

[Dave Philipsen]

I don’t see anything in the manual that describes exactly how the GIME maps out the row and column addresses to the DRAMs. And in most cases it would be fairly unimportant.  I’m assuming Jim was just noting his findings as a point of interest.

Most engineers will align A0->A0, A1->A1, etc. but it technically doesn’t matter which virtual address line goes to which physical memory address line as long as all different combinations produce all unique address locations in memory. The only reason I can think of for any concern over the matter would be if the refreshing method of the DRAM specifies a particular methodology.

So, Jim, if I understand correctly you are creating a 2MB memory expansion that will use the upper 2 unused bits in the MMU registers to access the entire 2MB, right?  Will your board use SRAM or DRAM?


Dave

>> On Sep 28, 2017, at 9:29 AM, RETRO Innovations <go4retro at go4retro.com> wrote:
>> 
>> On 9/28/2017 7:58 AM, Robert Gault wrote:
>> Jim,
>> 
>> This is outside of my area of knowledge but your description doesn't seem quite the same as that in the Coco3 service manual. I could be wrong. :)
>> 
>> Page 15-  Memory Management Unit (MMU)
>> This only deals with the stock 125K-512K addressing.
> The information on page 15 is correct, in that the top 3 bits of the virtual address are mapped to the top 6 bits of the physical address.  My information does not contradict that, it only states that the multiplexed address lines come out slightly different from the GIME.
>> 
>> Page 97  Pin layout and rough details of the inside contents of the GIME
> Can you be more specific?  I don't see any contradiction on first glance, but happy to be wrong.
>> 
>> Robert
> 
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