[Coco] FPGA VS Software Emulators

[Joel Rees]

On Tue, Jul 25, 2017 at 4:02 PM, Walter Zambotti <zambotti at iinet.net.au> wrote:
> Before I start this is not a one is better than the other debate.

> This is about better understanding each technology.
>
>
>
> Ok so my initial thoughts regarding FPGA (as I really know nothing) were
> hardware simulation should
> provide an end product that is more efficient and faster than a general
> CPU/software emulator.

There are lots of factors here. Be careful you are not trying to compare
grapefruit and kumquat.

> However this does not appear to be the case.
>
>
>
> The CoCo on a chip project emulates an 8mhz CoCo.

Cyclone® IV EP4CE22F17C6N FPGA

runs at 50 MHz.

> The CoCoFPGA project a 25mhz CoCo.

Altera Cyclone II 2C20 FPGA

runs at 50 MHz.

> And VCC on my i5 (3.3 ghz) a 133mhz CoCo.

> What causes these differences in end speed?
>
>
>
> Why are the two FPGA projects so different in speed?

Lots of possibilities -- differences between Cyclone IV and Cyclone II,
details of the specific parts chosen, other hardware on the board, the
development software they are using, the specific soft core chosen for
each, the way the MMU is implemented, ...

BTW, 25MHz CPU clock speed for a 6809 implemented in FPGA
running at 50 MHz is pretty impressive, especially with the MMU in
there.

> Why are both FPGA solutions slower than a CPU/software solution?

50 MHz is significantly less than 3.3 GHz. If VCC is emulating the
6809 at (average) 133 MHz, 3300/133 indicates the emulation routines
are taking an average of between 24 and 25 cycles per emulated op
code. That's also pretty tight for emulating in C code, BTW.  (Until you
consider what it costs us to support Intel's ability to put on a good show.)

> Is it the particular FPGA hardware itself?

Well, that is another question that has lots of answers. Maybe the
most interesting answer to you would be the design rules.

Design rules are about the size of individual transistors and wires
on the chip. Smaller transistors and shorter wires switch faster.

To a point, they also take less power at the same speed.

But higher speeds take more power, and the smaller size means the
CPU designers pack in a lot more stuff to squeeze a little more speed
out of Intel's patent portfolio for Intel's salescrew. That's part of the
reason your 3.3 GHz CPU consumes so much power.

So PFGAs actually consume less power than emulating that way.

Running the emulator on an ARM box would be interesting, but can
VCC run on something non-ARM?

> Would high end FPGAs provide a different result?

A faster FPGA is likely to produce a faster emulated CPU, but the
progammable nature of FPGA devices limits the possible speed.

> I've just download the FPGA for Dummies eBook from Altera so I'm starting my
> education process.

Have fun.

> Walter
>
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-- 
Joel Rees

One of these days I'll get someone to pay me
to design a language that combines the best of Forth and C.
Then I'll be able to leap wide instruction sets with a single #ifdef,
run faster than a speeding infinite loop with a #define,
and stop all integer size bugs with my bare cast.
http://defining-computers.blogspot.com/2017/06/reinventing-computers.html

More of my delusions:
http://reiisi.blogspot.com/2017/05/do-not-pay-modern-danegeld-ransomware.html
http://reiisi.blogspot.jp/p/novels-i-am-writing.html