[Coco] FPGA VS Software Emulators

tim franklinlabs.com tim at franklinlabs.com
Tue Jul 25 16:01:29 EDT 2017


   Yeah, agreed. I wrote a SDRAM controller running at 133MHz. using the
   on board Phase lock Loop. No problem

     On July 25, 2017 at 2:51 PM Dave Philipsen <dave at davebiz.com> wrote:

     Just adding to what James said: there isn't really an exact upper
     limit
     on the speed at which an FPGA will run. For instance, the DE1 board
     uses an on-board 50 MHz oscillator that can be used as a system
     clock
     but there are also PLLs that can generate a wide range of
     frequencies;
     some much higher than 50 MHz. I experimented on a DE1 once and
     actually
     created a VGA signal generator that put a nice solid 1280x1024
     colorful
     display on my monitor using a dot clock of over 100 MHz. However, it
     was a relatively simple design. I think when the design gets more
     complicated and the clock signals are being routed to numerous areas
     on
     the chip is when you start running into speed problems.

     Dave

     On 7/25/2017 2:31 PM, James Ross wrote:

     FPGA's are widely accepted to be a more accurate because the
     emulation it's done at the hardware electrical signal / logic gate /
     precise clock level timings. For all practical matter it *is* a
     hardware logic circuit.

     The speed issue w/ FPGA is probably two-fold.

     1) The FPGA must have an overhead of electrical logic that controls
     the pathways and configures the programmable gates and other logic
     blocks. That overhead probably affects the final speed of the
     device. Otherwise we would see 2 - 4 GHz devices - like we do CPU's

     2) The faster the FPGA the more expensive. So the 50MHz range is
     what is affordable for hobbyist and low budget digital electronic
     development. However, you can get faster for more $$$. I did a quick
     search, and the claim is made that the Intel Stratix IV is the
     fastest on the market w/ a Core Clock at 600MHz.

     With that said - I read a discussion about a software emulator used
     in a hardware context. Someone has a proof of concept / prototype of
     a 68020 (or higher) emulator running on an (cheap) ARM CPU off a
     small board w/ the IO's mapping to the 68020 pins and attaches to a
     real 68020 socket (I think it was an Amiga). If I can find that
     thread, on FB, I'll post it as a follow-up.

     In that case the software emulator is written to run on the
     bare-metal CPU. NO Operating System. The emulator controls the
     precise timing of everything running on the CPU. It's an interesting
     concept. I can see how it is possible. In that case you would not be
     able to tell the difference between a FPGA and a Software Emulator
     by just looking at (and precisely measuring) the output.

     James

     ________________________________________
     From: Coco <coco-bounces at maltedmedia.com> on behalf of Walter
     Zambotti <zambotti at iinet.net.au>
     Sent: Tuesday, July 25, 2017 7:02 AM
     To: 'CoCoList for Color Computer Enthusiasts'
     Subject: [Coco] FPGA VS Software Emulators

     Before I start this is not a one is better than the other debate.

     This is about better understanding each technology.

     Ok so my initial thoughts regarding FPGA (as I really know nothing)
     were
     hardware simulation should
     provide an end product that is more efficient and faster than a
     general
     CPU/software emulator.

     However this does not appear to be the case.

     The CoCo on a chip project emulates an 8mhz CoCo.

     The CoCoFPGA project a 25mhz CoCo.

     And VCC on my i5 (3.3 ghz) a 133mhz CoCo.

     What causes these differences in end speed?

     Why are the two FPGA projects so different in speed?

     Why are both FPGA solutions slower than a CPU/software solution?

     Is it the particular FPGA hardware itself?

     Would high end FPGAs provide a different result?

     I've just download the FPGA for Dummies eBook from Altera so I'm
     starting my
     education process.

     Walter

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