[Coco] 6809 FPGA Success
Bill Nobel
b_nobel at hotmail.com
Tue Sep 29 21:47:23 EDT 2015
Your right Dave, I just tried it at 25mhz and it works perfectly. And if I don't end up using the SRAM right away, I can reasonably play with this. I do have the SDCard sitting there and is in the build, but not wired yet.
Bill Nobel
> On Sep 29, 2015, at 7:42 PM, Dave Philipsen <dave at davebiz.com> wrote:
>
> Now you've got to figure out what to do with all of those extra LEs! The cores you are using now probably use less than 25% of your resources.
>
> Dave Philipsen
>
>> On Sep 29, 2015, at 8:23 PM, Bill Nobel <b_nobel at hotmail.com> wrote:
>>
>> Hey guys, (especially Dave, Roger and Mark) I have successfully got it fixed. I have Grants project running with 32k internal ram.
>>
>> The picture here still has the 512k SRAM on the breadboard, but is not used in this compile.
>>
>> https://www.dropbox.com/s/5tdly0g25w0dy22/IMG_0288.jpg?dl=0 <https://www.dropbox.com/s/5tdly0g25w0dy22/IMG_0288.jpg?dl=0>
>>
>> After taking note of Marks suggestions of the POR state. I took a closer look at the cores. John Kent’s code for the 6809 is covering the POR states (and is a newer version vs Gary Becker’s version for his Coco3FPGA).
>>
>> So I went back to the pin planner and discovered the Nano on GPIO-1, PIN-M10 is not on on bank 5 like the rest in the same area. I was using PIN-M10 for the videoB1 and that was causing my video instability. Changed it to PIN-N16 and everything works perfectly.
>>
>> Tanks for all your help guys….
>>
>> I am well on my way to really start to play with these things.
>>
>> Bill Nobel
>>
>>> On Sep 29, 2015, at 9:27 AM, Bill Nobel <b_nobel at hotmail.com> wrote:
>>>
>>> Hey Mark, Thanks for the pointers. I am using Grant’s code as is, just changed the pin assignments for the Nano. Looking at his clock code I can’t tell if he has a POR established. I just did a search on internet and found a few different ways it can be done. I have to check into these machine states that Altera has on the chips. I just found that out as I did the search. I will be looking at the reports more closely, as the searches gave me clues on where to look for power up states.
>>>
>>> Bill Nobel
>>>
>>>> On Sep 29, 2015, at 6:11 AM, Mark McDougall <msmcdoug at iinet.net.au> wrote:
>>>>
>>>> On 29/09/2015 12:59 PM, Bill Nobel wrote:
>>>>
>>>>> Most of the time when I program the Nano, I get a flaky VGA, it flashes
>>>>> the image in and out. When i get the image I can see what I typed, but
>>>>> very unstable display, until I get a good programming that boots
>>>>> properly.
>>>>
>>>> FPGA (ALtera Cyclone) bitstream packets are protected with CRC so it's very highly unlikely that the device is being configured with a corrupt bitstream, regardless of underlying OS layers.
>>>>
>>>> Not knowing anything about your design, I would actually suspect it could be an issue with your start-up logic. Are you generating a POR (power-on-reset) in your design and holding that for several hundred clocks (at least) to reset all the elements of your design?
>>>>
>>>> Regards,
>>>>
>>>> --
>>>> | Mark McDougall | "Electrical Engineers do it
>>>> | <http://members.iinet.net.au/~msmcdoug> | with less resistance!"
>>>>
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