[Coco] A Video Timing Question

[tim franklinlabs.com]

   OK, this is a "best practices" question for those working with FPGA
   video. My SOCoCo project is moving along. I got the CPU running in
   SDRAM and the video running on SRAM. However, I have struggled with the
   best method of syncing the CPU writes to the Video. I first tried a
   FIFO to delay the writes until the vertical and horizontal sync pulses.
   This worked but when I sped up the CPU to over 1MHz, with continuous
   writes, I was getting dropped character (sync times are too slow). Then
   I tried letting the CPU write to SRAM (still using a FIFO) and sync the
   writes within the reads of video (i.e. when data is ready to write I
   write instead of read). This method works well but I get sparkles on
   continuous CPU to video writes. I think that this is caused by the data
   going to the dac from the previous read cycle is actually delayed and
   held by the write cycle time.

   So, I'm wondering how others have addressed this?
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