[Coco] Kip's Single Board Computer

[Dave Philipsen]

To attempt to make it even clearer:  Normally, when the CPU puts an 
address on the address lines a memory device (ROM, RAM, etc.) responds 
by presenting data on the data bus (D0-D7).  When the CPU initially puts 
the reset vector address ($FFFE) on the address bus since there is no 
memory device out there the CPU will read the data that you have set up 
on the data lines (D0-D7).  If you permanently wire the data bus to be 
0x12 then that is all that can EVER be read from the data bus at ANY 
address....including the reset vector. First it will read the most 
significant byte (0x12) and then it will read the least significant byte 
(0x12).  Internally, these two reads are combined to form the address 
that will be loaded into the program counter for the reset which will be 
0x1212.  Then, the CPU will put 0x1212 on the address lines which won't 
really matter because there is no memory device out there to respond.  
But the CPU will believe that the first instruction and all subsequent 
instructions it receives are NOPs because the opcode for NOP is 0x12.  
Since NOP is a single byte opcode and a single cycle instruction the CPU 
will just move on to fetch the next instruction at an address one 
greater than the previous.  Again, it will find 0x12 there and thus 
execute a NOP.  Since the CPU is stepping through addresses one at a 
time because of the fact that the NOP is a single byte instruction you 
will see very regular patterns when you view the address lines on a 'scope.

Dave Philipsen


On 9/8/2015 7:23 PM, Dave Philipsen wrote:
> If you just pull up D2 and D5 this causes 0x12 to be present on the 
> data bus at all times.  Initially, when the CPU tries to fetch the 
> reset vector on startup it will see 0x12 as the high byte and the low 
> byte of the reset vector.  It will jump to address 0x1212 and will 
> again read 0x12 on the data bus which is a NOP.  Thereafter, all reads 
> of subsequent addresses (0x1213, 0x1214, etc) will come up with 0x12 
> so the CPU will just step through addresses one at a time at whatever 
> rate the core is clocked at.  If the CPU is clocked at 1 MHz you'll 
> see a 1 MHz waveform on A0, 500 KHz on A1, 250 KHx on A2, etc.
>
> Dave Philipsen
>
>
> On 9/8/2015 7:08 PM, camillus wrote:
>> I have to think a bit over this, so if there is no defined level on 
>> any of the address pins of the cpu and on the data bus the pattern 
>> 0x1212 is hardcoded, then the cpu will eventually read the dataport?
>>
>> Then how is it suppose to know from where to start fetching code. 
>> Without any address from where some code is to execute from the cpu 
>> is going wild, no?
>>
>> Or am I missing something?
>> ( maybe a brain...LOL )
>> cb
>>
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>> On 9/8/2015 6:46:39 PM, tim lindner <tlindner at macmess.org> wrote:
>> On Tue, Sep 8, 2015 at 4:29 PM, camillus wrote:
>>> Sorry I was not clear in my question, I was referring to the reset 
>>> vector. From where will the cpu start if there is no defined level 
>>> at 0xFFFE and 0xFFFF.
>>>
>>> Is there a hard coded address somewhere?
>>
>> If _all_ reads return 0x12, then the reset vector will be 0x1212. At
>> which point it will read 0x12 (nop).
>>
>>
>> -- 
>> -- 
>> tim lindner
>>
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