[Coco] 6809 FPGA

[Neal Crook]

1/ tap the caps-lock. Does the LED toggle? If so, your keyboard and its
FPGA interface are working fine and the problem is probably that the code
has crashed

2/ are you running the processor at 25MHz? If so, that is almost certainly
too fast for the external RAM. Try slowing it down to 5MHz while you debug

3/ do you have an SDC (timing) file in your FPGA project? If not, every
time you change and recompile the design you could get any variation in
timing.

4/ use both internal and external RAM as Mark suggests. They can "overlap":
you can enable them at the same time with no problem. The only thing you
need to do is to modify the blob of logic that creates the read data back
to the CPU, so that only one RAM drives back for each address region - you
should be able to see how to do this by studying Grant's "internal" and
"external" RAM designs. If you're stuck post your top-level RTL for review.
Put the internal RAM at the LOW address (start at 0) or BASIC will not find
it

4a/ with internal RAM working, use peek/poke from BASIC to try to infer
what's wrong with the external RAM: addressing fault, timing fault, data
fault, control fault

5/ write and ROM a tiny bit of code that makes no use of the stack but
simply takes the reset vector then sits in a loop reading, writing AA,
reading , writing 55 to 1 address. Use a scope or LSA or logic probe to
work out what's going on/wrong

6/ gotcha: ms basic walks through memory from 0 to size it. If you have RAM
all the way up to an I/O region, basic can stamp on the I/O -- which might
cause a problem. In Grant's design you hit ROM before I/O and so the sizing
routine stops.

7/ do an RTL simulation in Quartus. If you need help to set that up, hit
the "RTL Simulation" button in Quartus and report the first set of errors
that occur. If you're serious about RTL and FPGA you need to go through
this learning curve.

8/ check that your pin description file matches your physical hookup

9/ make sure you have good power/ground hookup to the RAM, and a decoupling
cap will never hurt, either.

10/ remember, debug IS the learning process (otherwise I'd just come right
out and tell you that you have a dry joint on pin 17)

Neal (just kidding about pin 17)

On 8 October 2015 at 05:18, Bill Nobel <b_nobel at hotmail.com> wrote:

> Hey Mark, so if I understand you correctly, do I enable both internal &
> external RAM at the same time?  Would that not cause memory overlap?
>
> Bill Nobel
>
> > On Oct 7, 2015, at 9:49 PM, Mark McDougall <msmcdoug at iinet.net.au>
> wrote:
> >
> > On 8/10/2015 2:44 PM, Bill Nobel wrote:
> >
> >> Hey all, as some of you know I have been porting Grant Searles
> >> project to my DE0-Nano.  I have it working with internal ram on the
> >> Nano itself with 32k ram.  I got my 512k SRAMs from Digikey a week
> >> ago, (wired as 64k)  when I try to use the SRAM instead of the
> >> internal RAM  I lose the PS/2 keyboard input.  I get the ‘6809
> >> EXTENDED BASIC’ banner, and ‘OK’ prompt. but no keyboard.  This is
> >> running it at 10mhz.  On internal RAM I can do 25mhz no problem.
> >>
> >> For the SRAM I have it going to IOBANKS 7 & 8. SRAM address bus &
> >> chip selects on bank 8 and SRAM data on bank 7.  Video & PS/2 I have
> >> on bank 5.
> >>
> >> Any suggestions would be helpful
> >
> > Have you tried your design running out of internal RAM but all the SRAM
> pin settings and driving logic in-place? What happens?
> >
> > Regards,
> >
> > --
> > |              Mark McDougall              | "Electrical Engineers do it
> > |  <http://members.iinet.net.au/~msmcdoug> |   with less resistance!"
> >
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