[Coco] FPGA 6809

Mon Aug 31 23:02:33 EDT 2015

Ok, I just figured out the problem.  Apparently Level2 shares a lot of 
Level1 stuff so, for instance, Boot and REL are found under Level1.  
They are not present under Level2.  On the other hand, there is 
apparently a different version of Krn for Level2 than for Level1 so one 
must go to the Level2 directory for that.  A little confusing but when 
you mentioned Level1 then I remembered and I looked in the source and 
there are no conditional statements for Level1/2....just a separate 
source for each one.

In my opinion it would be clearer just to go ahead and duplicate (in the 
Level2 directories) the Level2 stuff that is shared with Level1 so 
things don't get confusing for guys like me! :-)   But I suppose the 
makefiles take care of all that under Toolshed.

Dave Philipsen

On 8/31/2015 9:48 PM, Bill Nobel wrote:
> Also, Dave for asm under Nitros9 It is case insensitive where lwasm in the toolshed IS case sensitive on the labels. I have run into that issue as well. (branches especially don’t calculate offsets correctly)
>
> Bill Nobel
>
>> On Aug 31, 2015, at 8:40 PM, Dave Philipsen <dave at davebiz.com> wrote:
>>
>> Ahhh!   Maybe I should check that......
>>
>> Dave Philipsen
>>
>>> On Aug 31, 2015, at 9:19 PM, Bill Nobel <b_nobel at hotmail.com> wrote:
>>>
>>> I am doing pin planning as we speak.
>>>
>>> I just remembered while looking in the the source for os9.d D.MLIM, D.FMBM, etc… are Level 1 defs in direct page. are you setting Level2 equate?
>>>
>>> Bill Nobel
>>>
>>>> On Aug 31, 2015, at 7:46 PM, Dave Philipsen <dave at davebiz.com> wrote:
>>>>
>>>> Ok, so besides stripping all of the linefeeds and tabs I need to check for labels that are longer than eight characters.  That shouldn't be too tough to fix.  Right now, I'm assembling Boot with no errors and Krn is giving me a few; maybe 15-20.  I'll have to go look at the repo again. When I looked in the defs folder today (well at least ONE of the defs folders) the defs files I mentioned were nowhere to be found.
>>>>
>>>> Any progress on Multicomp-DE0?
>>>>
>>>> Dave Philipsen
>>>>
>>>>> On Aug 31, 2015, at 8:33 PM, Bill Nobel <b_nobel at hotmail.com> wrote:
>>>>>
>>>>> That would be the reason why.  The source in SourceForge is setup for Toolshed to be compiled on a pc.  The labels in the code are setup to be longer than 8 characters, which asm in Nitros9 ignores everything beyond.  Even if you get it compile you will get multiple define errors.  The DEFS files are in the repo under defs folder.
>>>>>
>>>>> Bill Nobel
>>>>>
>>>>>> On Aug 31, 2015, at 6:50 PM, Dave Philipsen <dave at davebiz.com> wrote:
>>>>>>
>>>>>> I don't think so.  To be totally honest I'm not exactly sure how that works.  I'm assuming that the fitter will assign pins for you if you don't manually assign them.  If you go into the Pin Planner it should show you a diagram of the FPGA and then below that there is a section where you can see all of the pin assignments. You should be able to scroll down to the bottom of that section and double click on <<new node>> to make a pin assignment.
>>>>>>
>>>>>> Quick question on NitrOS9:  Where are the defs files found in the repository?  I am using some defs files that someone else gave me on a boot disk image but when I try to assemble the Krn module it is choking on terms like "D.MLIM", "D.FMBM", "D.BTLO", and a few others.  I have fairly recent defsfiles (2011) and the defsfile uses os9defs, rbfdefs, scfdefs, and systype.  Am I missing anything?
>>>>>>
>>>>>> Maybe I'm crazy for assembling this directly under NitrOS9 but the assembler works pretty quickly at 25 MHz.  I don't have the cross assembler and the dev system set up on a PC.
>>>>>>
>>>>>>
>>>>>> Dave Philipsen
>>>>>>
>>>>>>
>>>>>>> On , Bill Nobel wrote:
>>>>>>> Would that be the fitter pins in the pin planner?  I saw those there
>>>>>>> and I thought it was a suggested pin.
>>>>>>> Bill Nobel
>>>>>>>> On Aug 31, 2015, at 4:30 PM, Dave Philipsen <dave at davebiz.com> wrote:
>>>>>>>> Just something else I thought of:  When starting a project out from scratch (i.e. CoCo3 or 6809 core on FPGA) there are some things to take into consideration when assigning pins to devices.  The Altera FPGAs are divided into physical banks and Altera suggests that the high speed signals such as address or data lines be grouped together within a bank or adjacent banks if at all possible.  Also, at least on some devices, there are certain banks that they consider more well suited for high speed stuff.  If you do a little research on the 'net you'll find some notes on this in the design considerations.
>>>>>>>> Dave Philipsen
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