[Coco] FPGA 6809

[tim franklinlabs.com]

   I agree with Mark on the comparisons with C code. FPGA code (vhdl or
   Verilog) doesn't run one line of code to the next as with most
   programming languages. It runs ALL lines of code at the exact same
   time. This can get confusing and can get you in to trouble if you think
   of it in the normal programming manner.

   Also, when it comes to bus control, you might want to look into the
   concept of a "wishbone" bus standard. Most open source FPGA code is
   using this as it's interface standard to allow one persons function
   blocks to easily interface with another.

     On August 31, 2015 at 7:17 AM Mark McDougall <msmcdoug at iinet.net.au>
     wrote:
     On 31/08/2015 3:18 PM, Dave Philipsen wrote:
     > It seems vhdl has some
     > similarities with C and as long as you have a mental picture of
     how the
     > schematic might look then perhaps writing vhdl code might get the
     job done a
     > little more quickly. Although, I can see where the schematic entry
     could
     > possibly be more accurate and less wasteful of logic elements. I
     was
     > communicating with Gary Becker who created the CoCo3 FPGA and he
     writes
     > everything in Verilog. He indicated that Verilog seems easier to
     work with
     > than VHDL.
     VHDL isn't much like C at all, Verilog is much more C-like. As for
     being
     easier than VHDL, that's a religious question and very subjective. I
     personally find VHDL much easier, although I have programmed in
     both. I
     actually find Verilog better for test benches which do not require
     that the
     resultant code be synthesizable.
     Schematic entry is usually preferred by HDL developers starting out,
     though
     some more experienced developers persist with it at the top level
     (only). I
     find it extremely inefficient to work with, tedious to maintain,
     impossible
     to manage in revision control software, and very non-portable across
     vendors. I steer well clear of it these days.
     As for being less wasteful; it you write your VDHL efficiently it
     won't be
     any different at all to the schematic version. And you can also view
     the
     synthesized VHDL design at the LE (gate) level if you really want
     to.
     Regards,
     --
     | Mark McDougall | "Electrical Engineers do it
     | <http://members.iinet.net.au/~msmcdoug> | with less resistance!"
     --
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