[Coco] I think now I have a final design

[Luis Antoniosi (CoCoDemus)]

That's the main difference between a FPGA and a convetional programming
approach.

On FPGA, everything runs on the clock beat, at the rising or falling edge.
There is no way to say: enough go to next pixel.

Also, the video is a stream of analog pulses. I cannot go to the next
pixel, I need to wait the time until the next pixel comes in, so the time
is sliced between 8 ticks, in fact I need 7 tests as i don't need to test
against 0V.

And FPGA is someway a combinational logic. If you put too many branches for
the same inputs, you create something very heavy or it just stops working.

I have 3 channels to read. Each channel is independent and I don't want to
have 3 different DACs. They must be tested at the very same time, so I made
a clock that will slice each pixel in 8.



Luis Felipe Antoniosi



On Wed, Nov 5, 2014 at 11:35 AM, Torsten Dittel <OS-9 at trs-80.cc> wrote:

> Hi Luis,
>
> I read on your page you need 8 steps for the 3-Bit ADC. Is that worst case
> and if the value is low it will be found earlier? Just out of curiousity:
> Why don't you use the successive linear approximation as e.g. being used
> for the CoCo 6-Bit ADC? E.g. reading the CoCo joystick needs always 6
> steps instead of 64 worst case if just incrementing the comparison voltage
> from 0 to 5 in 64 steps.
>
> Regards,
> Torsten
>
>
>
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