[Coco] Last video I promise... :)

[Sylvain Rousseau]

Hi,
If you have a very long combinational path, signals sync problem or speed problem with an FPGA may be the add of some pipelining may help you.
http://vhdlguru.blogspot.ca/2011/01/what-is-pipelining-explanation-with.html

Sylvain 

     Le vendredi 5 décembre 2014 20h48, Mark McDougall <msmcdoug at iinet.net.au> a écrit :
   

 On 6/12/2014 10:42 AM, Luis Antoniosi (CoCoDemus) wrote:

> I'll check that Mark, is that any book or document you suggest ?

This sort of thing is vendor-specific so you won't find it an any book. VHDL 
books I've seen don't even touch on the subject.

Best to read the TimeQuest doco, it's not too bad at all.

Regards,

-- 
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>  |  with less resistance!"

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