On 28/10/2013 12:22 PM, Mark J. Blair wrote: > except I'd use a > Xilinx FPGA instead of an Altera one Errk!! ;) (irrelevant, but FTR it's a CPLD) Regards, -- | Mark McDougall | "Electrical Engineers do it | <http://members.iinet.net.au/~msmcdoug> | with less resistance!"