[Coco] Nitros9 wd1773 boot code

[Gene Heskett]

On Saturday 13 July 2013 22:59:31 Robert Gault did opine:

> Matthew D Stock wrote:
> > I'm making a lot of progress on my wd1773 emulation, but I'm still
> > having problems with the nitros9 boot disks.  After looking at the
> > source code in boot_1773.asm, I have a question I'm hoping someone
> > can answer.
> > 
> > The issue is how the sector reads synchronize.  In the DECB ROM, there
> > is a tight loop that waits for the DRQ bit in the status register to
> > be high, and then it goes into the tight loop (with halt enabled)
> > that we all know and love. My code works fine there.
> > 
> > In the Nitros9 sector read code however, it looks like it relies on
> > some inherent timing and dispenses with the first status bit check
> > entirely. In fact, it looks like the code was there and someone
> > commented it out (see below).  My questions are: why was this sync
> > eliminated, and is there some known delay or (better) way to
> > synchronize that I haven't seen?
> > 
> > The code in question is pasted below.  Any help would be greatly
> > appreciated. Thanks,
> > 
> >    -Matt
> > 
> > L0107     stb   CONTROL,y
> > 
> >                  lbsr  Delay2        delay 54~
> >                  orb   #HALTENA        HALT enable ($80)
> > 
> > *              lda   #%00000010    RESTORE cmd ($02)
> > *L0111   bita  >DPort+STATREG
> > *              bne   L0123
> > *              leay  -$01,y
> > *              bne   L0111
> > *              lda   drvsel,u
> > *              sta   >DPort+CONTROL
> > *              puls  y
> > *              bra   L0138
> > 
> >                  stb   CONTROL,y
> >                  nop
> >                  nop
> > 
> > *              bra   L0123
> > 
> >                  ldx   ,s            get X saved earlier
> > 
> > * Sector READ Loop
> > L0123     lda   DATAREG,y    read from WD DATA register
> > 
> >                  sta   ,x+
> > 
> > *              stb   >DPort+CONTROL
> > 
> >                  nop
> >                  bra   L0123
> 
> If you look at the rb1773.asm code in the level1/modules directory you
> will find comments about this section. There had been a problem (BLOB)
> with booting named the Boot List Order Bug. You ought to be able to
> read about it somewhere on RTSI. People used to think that you had to
> rearrange the module order but someone found that the code above was
> bad. The is no need to continuously send code to the controller in loop
> L123. The code around L0111 is not needed.
 
The BLOB?  AFAIK This code has zero to do with that Robert, it was a one 
command fix in the all the clock modules (which contains the IRQ detection 
and service discovery routines) to properly re-enable the GIME's response 
to an IRQ after servicing a previous one.  You can read the rational about 
that in the blobstop files, should be on rtsi, and in the texts of 
BlobStop.lzh on my site, link in sig.
 
> 
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Cheers, Gene
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