[Coco] 6309/6809 opcodes with mixed 8/16 bit registers

[Harry Hurst]

Lately, I've been cleaning up some of the clutter that I've accumulated,
and I've run across a lot of stuff that I had forgotten about. One of them
was a simulator for the 6x09 that I started back in '90. I think I'd like
to finish it so I started looking it over a bit. I've found some errors,
but the biggest problem I have presently is info on what happens when the
two CPU's when they encounter the unexpected. On the 6309 I know there is
a trap for invalid opcodes that takes it to the vector stored in $FFF0.
(It also sets MD.6 so it can be distinguished from a divide by 0 trap,
which shares that vector) So here are my most pressing questions:

1> Does the 6809 just execute an effective NOP on an illegal opcode? Or
does it decode the illegal opcode as a nearby opcode?

2> Does anyone have any info on what would happen if a 6x09 would execute
opcodes like TFR or EXG with mixed 8 and 16 bit registers specified? Do
both the 6809 and the 6309 behave the same in this case?

3> What happens on the 6309 when it has mixed 8/16 bit operands on the
ADCR, ADDR, ANDR, EORR, etc.?

4> Do invalid indexing modes also trigger the invalid opcode trap on the
6309?

I'll be using debug to test some of these conditions, but it would be
great if I could get some of the answers from someone who already knows
them. Thanks,

HH