[Coco] 6809 / General CPU question

[John Kent]

Mike,

 From what I described, it still fetches the reset vector from ROM.

Looking at the specification sheet for the SAM chip a few weeks back, I 
think it remapped the interrupt and reset vectors accessed by the CPU at 
$FFF2 - $FFFF down to one of the ROMs located lower in memory. The 
vectors are still in ROM but they are mapped up to $FFF2 - $FFFF. The 
SAM does some decoding or remapping of the address range and uses a 1 of 
8 decoder on the S0,S1 and S2 outputs to generate the ROM and RAM chip 
selects. There are registers mapped near the top of memory in the SAM, 
but there is a hole in the decoding at the top for the vector remapping. 
The register bits in the SAM are set or cleared by reading or writing to 
different memory locations. These affect the RAM decoding as I recall 
and the VDG memory address offset and some of the VDG functions (?). 
There is no data bus on the SAM due to the fact that they use a 40 pin 
DIP chip and it has to have address buses for the CPU, VDG and DRAM 
chips that uses up most of the pins.

I'm not really that familiar with the CoCo3 layout, but I assume the SAM 
(and VDG ?) is replaced by the GIME chip that adds extra functionality 
such as extended memory addressing.

John.

On 21/02/2011 2:25 AM, Mike Rowen wrote:
> I think what may have caused me to come up with this question in the first
> place is that I am studying the 6809 and 6809 machine language. I was
> looking at a memory map of the CoCo and these addresses (FFFE&  FFFF) appear
> to be in an area called "Dedicated Addresses" and it seems outside of the
> addresses mapped to various ROM locations. So I ruled out ROM being mapped
> to these the addresses. That may or may not be the case. If it isn't in
> ROM,it is likely that it is done through other address mapping on the
> hardware, much as John describes. What I have learned through all of the
> discussion is that the 6809 indeed needs to get its starting point by
> looking at FFFE&  FFFF. What is mapped to these addresses appears to be
> strictly up to the computer designer. I have a Simon6809 and on that
> computer, these addresses (FFFE&  FFFF) are clearly ROM locations. From a
> computer user perspective, the exact mechanism of this is completed before
> you could do anything meaningful on the system. On both a CoCo or Simon6809,
> you can't write to these locations.
>
> I'm glad I asked this question as it really helps me appreciate the
> complexities of hardware and all of the critical timing involved. It
> certainly reveals the elegance of system design. While learning 6809 ML, I
> can see how much more one needs to know about all of the combined hardware
> to write a Space Intruders or Zaxxon! My hats are off to all of you with
> that level of knowledge. Thanks everyone for your replies!
>
> Regards,
> -Mike Rowen
>
>
>
> On Sun, Feb 20, 2011 at 1:49 AM, John Kent<jekent at optusnet.com.au>  wrote:
>
>> I suspect the vector is read into a temporary internal register then
>> transferred to the program counter as the program counter is used to fetch
>> the vector or at least it can be. The program counter would have to be
>> pre-initialized with all 1's in the high address bits and a interrupt vector
>> offset in address bits A3 to A1 on reset. I don't know if that is how
>> Motorola did it. I was a bit concerned about patents, but I think they have
>> all expired, so I don't think I'm violating anyone's patent. I'm certainly
>> not making any money out of it.
>>
>> John.
>>
>>
>>
>> On 20/02/2011 10:46 AM, Mike Rowen wrote:
>>
>>> Thanks everyone for your responses. Ok, so whenever the CPU powers on or
>>> experiences a RESET inturrupt, the CPU will read the contents of FFFE&  FFFF
>>> and load it into the program counter register. It then fetches instructions
>>> from that location. Presumably this would be a location in ROM.
>>>
>>> How does an address get into FFFE&  FFFF when the system is initialized?
>>> Is this through hardware? Are these RAM locations?
>>>
>>>
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