[Coco] 6x09 read and write strobes.

[John Kent]

Falling edge of Q is it ?
I posted a timing diagram, on 2011/12/05 but I must have had Q inverted.

You can use a 7400 to generate read and write strobes, or half a 74139 
decoder.
Phil was using a CPLD and verilog to program it.
The equations he used were:

assign RD            = E & RW & Reset;
assign WR            = Q & ~RW & Reset;
assign nRD            = ~RD;
assign nWR            = ~WR | RamWP;

what it should have been I think was:

assign RD            = E & RW & nReset;
assign WR            = E & ~RW & nReset;
assign nRD            = ~RD;
assign nWR            = ~WR | RamWP;

I'm not sure if his reset was active high or active low.
I have not used verilog much, so I'm not 100% sure of the syntax.
Some peripherals such as the Z8530 assert both RD & WR to reset the 
peripheral, if my memory serves me correctly. I'm not sure if Phil was 
trying to do that or if he was trying to prevent random read/writes 
during reset.

I didn't get a reply from Phil Harvey-Smith, so I'm not sure if he has 
sorted out his problem.

John.


On 16/12/2011 1:13 PM, jdaggett at gate.net wrote:
> Phil
>
> Not sure if this is too late or not.
>
> The 6809 use the E clock to primarily sync with peripherals as well as internal uses. The Q
> clock is an internal clock. The address bus as well as the RW line are all valid on the falling
> edge of the Qclock after the falling edge of the Eclock. The falling edge of the Eclock starts a
> new cycle. You can generate an Intel compatible Write enable output by inverting the RW line
> and NANDing it with the Eclock.  A comparable Output Enable read signal is just NANDing
> the RW line with the E clock.
>
>
> james
>

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