[Coco] What would a CoCo successor have to have as a minimum?

[John Kent]

On 21/11/2010 2:49 PM, John Kent wrote:
> I might also add that the software emulator has to perform memory 
> decoding, bounds checking and memory mapping all sequentially. It also 
> has to emulate the hardware, which is presumably on an an I/O space 
> access, but may also be concurrent with the (emulated) CPU execution. 
> The FPGA does this all in parallel. So even if there are say 100 (PC) 
> CPU cycles to one FPGA (emulated CPU) clock cycle there is a lot the 
> (PC) CPU has to do in those 100 cycles.
>
>
> On 21/11/2010 2:05 AM, John Kent wrote:
>>
>>
>> FPGAs are much slower than you average PC with clock speeds around 
>> 100MHz as opposed to 2 or 3 GHz, however, The FPGA can be 
>> incrementing the Program Counter of the 6809 at the same time as it's 
>> performing some ALU function or calculating a register offset.  Also 
>> the PC has to execute multi-cycle instructions to interpret the 6809 
>> instruction, (albeit piplelined) so even with the most optimized 
>> assembler code, you are talking about many cycles and many 
>> instructions to do what the FPGA does in one cycle.
>>
>>
>

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