[Coco] What would a CoCo successor have to have as a minimum?

[John Kent]

Hi John.

Would the CPLD include the memory controller logic, or would you rely on 
the SAM in the CoCo to do the refresh ?
I would have thought that the wider column would mean that it would need 
it's own refresh counter.
There is also all sorts of initialization sequences to set up burst 
length and access timing and so on.

I have wanted to play with Xilinx CPLDs. There operate of 5V and you can 
get them in PLCC packages. (It's easier for me to solder a plate through 
PLCC socket as opposed to a QFP). I would imagine though that to 
implement the memory controller you'd need a fairly large CPLD, and 
you'd have to multiplex the 32 bit data bus onto a 8 bit CoCo bus. You'd 
also probably need some way of buffering the SDRAM data so that it could 
be randomly accessed by the CoCo.  i.e. You'd have to hold the processor 
if you wrote to SDRAM during a refresh cycle.

John.

On 21/11/2010 2:14 PM, Little John wrote:
> There are two sets of task registers, 8 bytes each with the TR bit 
> determining which of the two is active :-)
> I can provide you with all of the design details. I doubt that I would 
> ever get around to building it - but I may one day - it would require 
> way too many 30 pin simms, so I'm having to design with 72 pin simms 
> which could theoretically max it out with 4 modules of 128MB. I was 
> going to stick the whole thing in a Xilinx CPLD...
> -John also ;)

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