[Coco] CoCo 1&2 clock cycle events (CPU, SAM, VDG interaction with RAM)

[Willard Goosey]

On Mon, May 24, 2010 at 09:49:31PM +0200, Fedor Steeman wrote:

> As the 6809 (normally) operates at 0.89 MHz, I can calculate the duration of
> a single E-clock wave (i.e. rise and fall), ought to be 1124 nanoseconds.

You'd either have to measure it, or get the exact frequency of the
crystal and know exactly what the SAM(?) does with it to generate E & Q.
> 
> According to the reference manual, however, the duration is apparantly 1117
> nanoseconds:

That's .8952 MHZ, close enough for advertisers.  
> 
> http://www.bighole.nl/pub/mirror/homepage.ntlworld.com/kryten_droid/coco/coco_tm_18.png

> I really cannot make sense of this diagram, as there are two other numbers,
> 629 ns og 488 ns, that add up to 1117, but there start and end points seem
> to drawn wrongly.

There are setup times.  At the nanosecond scale, it takes time for a
signal to change.  I was just looking at the timing for the 2MHz
68HC11 (pretty much the same bus design as the 6809, minus the Q
clock) and it expects that the maximum time it takes for E to change
state is 25 ns.

> Does this mean that the low section of the E clock has a shorter duration
> (488 ns) than the high section? 

Apparently.  Interesting, yes?
> 
> I just want to know who long this cycle takes and each of its steps:

I don't have the timing diagrams for the CoCo 1 & 2, so I can't speak
for the SAM and VDG... but..


half-way between E-low & Q-high: CPU sets RAM address. (SAM may
intecept this while it does its own thing)

>         E-high & Q-low: CPU reads/writes RAM byte
Right.
> 
> Thanks for any help...

OK, your CPU timing chart in ASCII (from the above url).....

     |------------1117ns-------------------|
E----\______________________/---------------\______
      |--------629ns-------| |-----488ns----|
      |----279ns-----|
Q___________________/-------------\_______________
R/W*_______/-------------------------------------
ADR===XXXXX=====================================
DAT-------------------------------XXX<valid=>----

E takes 1117 ns for a full cycle.
It takes an unlisted time to fall, is 0 for 629ns.
E takes an unlisted time to raise, and is 1 for 488ns
(It would be nice if they specified how long Q is high)

279ns afer E has finished falling, Q has finished changing to 1.
By that time, R/W* (read or write), and the address are both valid and
stable.

After Q falls, the data bus is valid and stable.

T=0ns: E is low.
T approximately 100ns: R/W* and Address valid.
T=279ns: Q is high
T=629ns: E goes high
T approx. 830ns: Q goes low.
T approx. 850ns:  data bus valid.
T=1117ns: E goes low.  Cycle repeats.

Did that help?  I'm afraid I'm not very good at explaining things.

Willard
-- 
Willard Goosey  goosey at sdc.org
Socorro, New Mexico, USA
I search my heart and find Cimmeria, land of Darkness and the Night.
  -- R.E. Howard