[Coco] 6309 Interrupt Timing

[jdaggett at gate.net]

Darren

At least for the 6809  and for the 6309 running in 6809 mode, the interrupts are not latched in 
until after the HALT is processed and before opcode fetch. This will be at the start of every 
instruction prior to opcode fetch. 

The RESET, HALT, NMI, FIRQ, and IRQ pins have debounce circuits in line. This takes at 
least one machine cycle to ripple through. Also this rippling through the debounce circuit 
must be completed on machine cycle before the LIC pulse becomes active. If the interrupts 
are latched in during the last cycle of an instruction then it will not be acknowledge until the 
next cycle. That is because the 6809 has already incremented the PCR and is ready to latch 
it out to the address bus. There is a dead cycle also after HALT, SYNC and I believe CWAI 
for reasons to allow the PCR to be properly loaded with the correct address and ready to 
output to the bus. 

james

On 20 Jun 2010 at 11:02, Darren A wrote:

> I just encountered another difference between a 6309 running in native
> mode versus emulation mode which I haven't seen mentioned before.  It
> has to do with interrupt timing.
> 
> The 6809 imposes a one-cycle delay from the latching of an interrupt
> (NMI, IRQ or FIRQ) before it will respond.  This means when an
> interrupt is latched during the last cycle of an instruction, the
> service routine will not be invoked until after the *following*
> instruction has completed.
> 
> The 6309 behaves the same way when running in emulation mode but not
> in native mode.  No delay is imposed in native mode.  This makes sense
> since many instructions will execute in one cycle under native mode.
> If the delay were to occur, you could not use NMI to implement a
> hardware assisted single-stepper.
> 
> I would imagine that HALT is similarly affected, although I haven't
> actually tested that.
> 
> Darren
> 
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