[Coco] Interesting reading

[jdaggett at gate.net]

A while back I was doing some patent searches and came across several Motorola Patents 
on the 6800 series processors. I also came across two other patents that covered the FIRQ 
function. 

Well today I really started in depth reading of one patent. Well needless to say it is been very 
educational. Figure #7 of the design and the corresponding description of it is enlightening on 
how the hardware inputs work. From everything I read the embodiement processor for the 
invention is the MC6809. No other processor of that time had Reset, Halt, NMI, FIRQ and 
IRQ external hardware inputs. Patent US-4200912, Processor Interrupt System, describes 
much of the logic behind the MC6809 interrupt system and how it works. 

I have gathered this from the patent. There is a priority assigned to the external inputs. They 
are as follows:

RESET   1 (highest)
HALT	   2
NMI	   3
FIRQ      4
IRQ        5  (lowest)

Also the priority circuit allows for an asychronous reset to occur and if in HALT mode, once 
the HALT input is released a RESET occurs. 

So far I have gained even a better insight on the vernable old processor. All this started 
recently because I wanted a cycle accurate 6809/6309 processor for a project I have. I also 
want to put it in an FPGA for increased speed and lower voltage operation. Hopefully battery 
operation capable. 

This has been very educational and fun read. I still need to decipher more.  Also if figure #2 is 
correct in the patent, then the 6809 has two 8 bit data buses along with the two  8 bit address 
buses. That would explain a lot of how movement of data could be done without a huge 
amount of buss switches or multiplexors. 

Now I have a better idea on how to code the HDL and hopefully a cycle accurate processor 
can come out of it. Eventually a 6309 capability also. I think I am about to move this project 
up the priority ladder now. ( no pun intended)

more as I get further along. 

james