[Coco] Multi-Pak card edge connectors.

[jdaggett at gate.net]

Brian

I will be interested in your layout. I have quite an extensive experience in PCB layout and 
design.

james

On 16 Jan 2010 at 6:02, Brian Blake wrote:

> Only if one has expeience with them. I haven't chased trons since 1995 when I got out of the Navy. My goal for this project was to successfully duplicate something someone else has done and learn from it. I have no experience with CPLDs and think I'd probably have a lot of problems doing a conversion like that. 
> 
> At least with this approach I can look at the individual datasheets and have some idea of what output to expect with a given input.
> 
> With a CPLD I'll have learn to program that and then troubleshoot all my mistakes on top of that... Not a fun time for a first project. I could doing this when I get more experience.  
> 
> Sent from Brian's iPhone
> 
> On Jan 15, 2010, at 5:43 PM, jdaggett at gate.net wrote:
> 
> On 15 Jan 2010 at 7:19, Brian Blake wrote:
> 
> 
> 
> Heh... And I was referring to my PCB layout I'm working... Can't wait to see you guys tear that apart, lol... And yes, I'll take it in stride because I'm new at this and I want the damn thing to work, lol!!!
> 
> I did ask Tom about the S parts he has called out - he said he had prblems when he used the LS variants...
> 
> 
> Brian
> 
> |===================
> 
> After looking at his schematic I can understand why. Trying to do what is done in the PAL 
> chip with discrete logic adds a couple of layers of logic and the associated propogation 
> delays along with fan out issues. There are only two Schotky devices in the schematic. 
> Twenty discrete logic ICs? All that can now be done easily in a CPLD. 
> 
> james
> 
> 
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