[Coco] lbsr and rts

[William Astle]

Wayne Campbell wrote:
> There are still things I don't get, like why, in some cases, LDD is followed by a single byte, but in other cases it is followed by a byte and an integer. The syntax of the instruction doesn't give me any clues, yet. (Lack of understanding on my part)

This, I think I can clear up for you.

Each instruction (LDD, JSR, LBSR, INCA, etc.) has one or more addressing
modes. An addressing mode describes how the instruction obtains its
operand. There are several modes:

Inherent: this is where the operand is "inherent" to the instruction.
INCA, for instance, includes its operand in the instruction code. RTS is
also "inherent" because it doesn't require an operand.

Direct: (sometimes called "base page" or "direct page") this mode
obtains its operand from memory by taking the value in the DP register
as the upper 8 bits of the address and the byte following the opcode as
the low 8 bits of the address. (So if DP has $14 and the instruction
byte is $11, the address would be $1411.) Direct addressing is often
represented by prefixing the operand with a "<".

Extended: In this mode, the entire 16 bit address of the operand is
specified following the opcode. Extended addressing is often represented
by prefixing the operand with a ">".

Indexed: This is a collection of addressing modes that work off of index
registers (X, Y, U, S, PC). It's quite complex. An indexed instruction
will have between 1 and 3 bytes following the opcode, the first of which
 (the post byte) determines the actual indexed mode. Some modes are 8
bit offsets where the offset follows the "post byte". Some modes are 16
bit offsets where the offset follows the post byte. 8 bit offsets are
often prefixed with "<" and 16 bit offsets are often prefixed with ">".
Note that all indirect addressing modes are indexed. (Indirect is
indicated by enclosing the operand in "[" and "]"). More on this below.

Extended Indirect: This is a special case of indexed addressing that
does not reference an index register. In this case, the opcode will be
followed by 3 bytes - a post byte specifying extended indirect and a 16
bit address.

Immediate: This is where either 8 bits or 16 bits of data follows the
opcode, depending on the size of the register involved. (So 8 bits for
A, B, or CC and 16 bits for D, X, Y, and U.) Immediate mode is always
identified by prefixing the operand with a "#".

Relative: all Bxx and LBxx instructions are relative. The "LBxx"
variations use a 16 bit offset while the non "L" versions use an 8 bit
offset.

Misc: there are two miscelaneous types of instructions. PSH/PUL and
TFR/EXG. Both take a single post byte. The former interprets it as a
bitmap to determine which registers to push or pull. The latter breaks
it into two nibbles to determine the first and second register operands.

Most instructions support multiple modes. Each mode has its own opcode
which is how the CPU tells them apart. Let's pick on LDD. The various
opcodes are:

Immediate mode: $CC
Direct mode: $DC
Indexed mode: $EC
Extended mode: $FC

All of the above will be represented by "LDD" in source code.

Another example would be JSR:

Direct mode: $9D
Indexed mode: $AD
Extended mode: $BD

All of the above will be represented by "JSR" in source code.

Identifying addressing modes is actually easier than it looks. The
following steps may help when examining a source listing. Bail out at
the first match:

1. If the instruction is PSHS, PULS, PSHU, or PULU, it's a register list
2. If the instruction is EXG or TFR, it's a pair of registers
3. If the instruction is LBxx, it is 16 bit relative
4. If the instruction is Bxx, it is 8 bit relative
5. If the operand starts with a "#", it's immediate mode.
6. If the operand contains a ",", it's indexed.
7. If the operand is enclosed in [ and ], it's extended indirect (which
is a subset of indexed. In fact, it's the only indexed mode that does
not contain a comma.)
8. If the operand starts with a "<", it's direct
9. If the operand starts with a ">", it's extended
10. It may be either direct or indirect. You will not likely see this in
output from a disassembler. In this case, the assembler makes a guess
about whether Direct of Extended mode is required based on what it
thinks the DP register is set to. (SETDP is how it learns this. SETDP is
NOT an actual 6809 instruction; it does not actually set the DP
register. The only way to do that is with TFR or EXG.)

There is quite a lot of variation with the indexed modes. A good
reference on the indexed modes of the 6809 will help sort that out.